dt-bindings: nand: denali: reduce the register space in the example

Message ID 1505373456-24047-1-git-send-email-yamada.masahiro@socionext.com
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  • dt-bindings: nand: denali: reduce the register space in the example
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Commit Message

Masahiro Yamada Sept. 14, 2017, 7:17 a.m.
This example allocates too much for register regions.  Especially,
there are only two registers in the "nand_data" interface of this
hardware (ADDR: 0x00, DATA: 0x10).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 Documentation/devicetree/bindings/mtd/denali-nand.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Oleksij Rempel Sept. 14, 2017, 8:04 a.m. | #1
Hi,

i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?

On 14.09.2017 09:17, Masahiro Yamada wrote:
> This example allocates too much for register regions.  Especially,
> there are only two registers in the "nand_data" interface of this
> hardware (ADDR: 0x00, DATA: 0x10).
> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
> 
>   Documentation/devicetree/bindings/mtd/denali-nand.txt | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt
> index 504291d..0ee8edb 100644
> --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt
> @@ -29,7 +29,7 @@ nand: nand@ff900000 {
>   	#address-cells = <1>;
>   	#size-cells = <1>;
>   	compatible = "altr,socfpga-denali-nand";
> -	reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
> +	reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
>   	reg-names = "nand_data", "denali_reg";
>   	interrupts = <0 144 4>;
>   };
> 
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Masahiro Yamada Sept. 14, 2017, 8:16 a.m. | #2
Hi.


2017-09-14 17:04 GMT+09:00 Oleksij Rempel <ore@pengutronix.de>:
> Hi,
>
> i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?

I think so.
(also arch/arm/boot/dts/socfpga_arria10.dtsi in the same way)

The wrong property "dma-mask" was removed by
commit 60d920d32ca40660e382cf9ccbc236599a49e607.



> On 14.09.2017 09:17, Masahiro Yamada wrote:
>>
>> This example allocates too much for register regions.  Especially,
>> there are only two registers in the "nand_data" interface of this
>> hardware (ADDR: 0x00, DATA: 0x10).
>>
>> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>> ---
>>
>>   Documentation/devicetree/bindings/mtd/denali-nand.txt | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt
>> b/Documentation/devicetree/bindings/mtd/denali-nand.txt
>> index 504291d..0ee8edb 100644
>> --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
>> +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt
>> @@ -29,7 +29,7 @@ nand: nand@ff900000 {
>>         #address-cells = <1>;
>>         #size-cells = <1>;
>>         compatible = "altr,socfpga-denali-nand";
>> -       reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
>> +       reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
>>         reg-names = "nand_data", "denali_reg";
>>         interrupts = <0 144 4>;
>>   };
>>
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Oleksij Rempel Sept. 14, 2017, 9:06 a.m. | #3
On 14.09.2017 10:16, Masahiro Yamada wrote:
> Hi.
> 
> 
> 2017-09-14 17:04 GMT+09:00 Oleksij Rempel <ore@pengutronix.de>:
>> Hi,
>>
>> i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
> 
> I think so.
> (also arch/arm/boot/dts/socfpga_arria10.dtsi in the same way)

Hm.. according to
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
Table 13-18: NAND Controller Module Data Space Address Range

Module Instance       Start Address        End Address
NAND_DATA             0xFF900000           0xFF9FFFFF

So <0xff900000 0x100000> seems to be a proper value.

> The wrong property "dma-mask" was removed by
> commit 60d920d32ca40660e382cf9ccbc236599a49e607.
> 
> 
> 
>> On 14.09.2017 09:17, Masahiro Yamada wrote:
>>>
>>> This example allocates too much for register regions.  Especially,
>>> there are only two registers in the "nand_data" interface of this
>>> hardware (ADDR: 0x00, DATA: 0x10).
>>>
>>> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>>> ---
>>>
>>>    Documentation/devicetree/bindings/mtd/denali-nand.txt | 2 +-
>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt
>>> b/Documentation/devicetree/bindings/mtd/denali-nand.txt
>>> index 504291d..0ee8edb 100644
>>> --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
>>> +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt
>>> @@ -29,7 +29,7 @@ nand: nand@ff900000 {
>>>          #address-cells = <1>;
>>>          #size-cells = <1>;
>>>          compatible = "altr,socfpga-denali-nand";
>>> -       reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
>>> +       reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
>>>          reg-names = "nand_data", "denali_reg";
>>>          interrupts = <0 144 4>;
>>>    };
>>>
>> --
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>> the body of a message to majordomo@vger.kernel.org
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> 
> 
> 
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Masahiro Yamada Sept. 21, 2017, 5:26 a.m. | #4
Hi.


2017-09-14 18:06 GMT+09:00 Oleksij Rempel <ore@pengutronix.de>:
> On 14.09.2017 10:16, Masahiro Yamada wrote:
>>
>> Hi.
>>
>>
>> 2017-09-14 17:04 GMT+09:00 Oleksij Rempel <ore@pengutronix.de>:
>>>
>>> Hi,
>>>
>>> i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
>>
>>
>> I think so.
>> (also arch/arm/boot/dts/socfpga_arria10.dtsi in the same way)
>
>
> Hm.. according to
> https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
> Table 13-18: NAND Controller Module Data Space Address Range
>
> Module Instance       Start Address        End Address
> NAND_DATA             0xFF900000           0xFF9FFFFF
>
> So <0xff900000 0x100000> seems to be a proper value.
>

The Alrera's SOCFPGA document describes so.
It is up to each SoC vendor how to describe the register space.

I am focusing on the Denali IP
because this IP is used among several SoCs.



You can see the peripheral region map
starting at page 1-18 of the document you referred to:

Slave ID      Description                  Base Addr      Size
---------------------------------------------------------------
L3REGS        L3 interconnect GPV          0xFF800000      1 MB
NANDDATA      NAND flash controller data   0xFF900000     64 KB
QSPIDATA      Quad SPI flash data          0xFFA00000      1 MB

(In the doc, the base is described as 0xFFB900000, but this is
apparently a typo.)


The rationale of the "End Address 0xFF9FFFFF" of NAND_DATA
is the fact that the base address of the next peripheral (QSPIDATA) is
0xFFA00000.




One more, if you look at the next page,

Slave ID      Description                      Base Addr     Size
---------------------------------------------------------------
NANDREGS      NAND flash controller registers   0xFFB80000   64 KB
FPGAMGRDATA   FPGA manager configuration data   0xFFB90000    4 KB


The size of NAND register space is described as 64KB,
but the rationale is just the start of the next peripheral is 0xFFB90000.

(0xFFB90000 - 0xFFB80000 = 0x10000 = 64KB)



Altera apparently reserved address space just for the purpose
of matching the end address to the base address of the next peripheral.


That means, this document specifies address region
much bigger than the IP actually provides.


If you look at page 13-6, there are only two registers
in NANDDATA space.

Table 13-4: Register Map for Indexed Addressing
Control   0x0
Data      0x10



For NANDREGS, in page 13-106, the following is the last register
in the NANDREGS space.

lun_status_cmd
Offset 0x7A0

Obviously, 0x1000 (4KB) is enough for NANDREGS.





To conclude this, this binding document was written
based on the Altera's SOCFPGA specification.

Altera specifies the region size
so that end address matches to the base of the next peripheral.
This is just a matter of SOCFPGA address mapping.

In my opinion, the binding document should not be oriented
to a particular SoC, which is not true for other SoCs.
Oleksij Rempel Sept. 21, 2017, 6:09 a.m. | #5
Hi,

On 21.09.2017 07:26, Masahiro Yamada wrote:
> Hi.

......
>> Hm.. according to
>> https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
>> Table 13-18: NAND Controller Module Data Space Address Range
>>
>> Module Instance       Start Address        End Address
>> NAND_DATA             0xFF900000           0xFF9FFFFF
>>
>> So <0xff900000 0x100000> seems to be a proper value.
>>
> 
> The Alrera's SOCFPGA document describes so.
> It is up to each SoC vendor how to describe the register space.
> 
> I am focusing on the Denali IP
> because this IP is used among several SoCs.
> 
> 
> 
> You can see the peripheral region map
> starting at page 1-18 of the document you referred to:
> 
> Slave ID      Description                  Base Addr      Size
> ---------------------------------------------------------------
> L3REGS        L3 interconnect GPV          0xFF800000      1 MB
> NANDDATA      NAND flash controller data   0xFF900000     64 KB
> QSPIDATA      Quad SPI flash data          0xFFA00000      1 MB
> 
> (In the doc, the base is described as 0xFFB900000, but this is
> apparently a typo.)
> 
> 
> The rationale of the "End Address 0xFF9FFFFF" of NAND_DATA
> is the fact that the base address of the next peripheral (QSPIDATA) is
> 0xFFA00000.
> 
> 
> 
> 
> One more, if you look at the next page,
> 
> Slave ID      Description                      Base Addr     Size
> ---------------------------------------------------------------
> NANDREGS      NAND flash controller registers   0xFFB80000   64 KB
> FPGAMGRDATA   FPGA manager configuration data   0xFFB90000    4 KB
> 
> 
> The size of NAND register space is described as 64KB,
> but the rationale is just the start of the next peripheral is 0xFFB90000.
> 
> (0xFFB90000 - 0xFFB80000 = 0x10000 = 64KB)
> 
> 
> 
> Altera apparently reserved address space just for the purpose
> of matching the end address to the base address of the next peripheral.
> 
> 
> That means, this document specifies address region
> much bigger than the IP actually provides.
> 
> 
> If you look at page 13-6, there are only two registers
> in NANDDATA space.
> 
> Table 13-4: Register Map for Indexed Addressing
> Control   0x0
> Data      0x10
> 
> 
> 
> For NANDREGS, in page 13-106, the following is the last register
> in the NANDREGS space.
> 
> lun_status_cmd
> Offset 0x7A0
> 
> Obviously, 0x1000 (4KB) is enough for NANDREGS.
> 
> To conclude this, this binding document was written
> based on the Altera's SOCFPGA specification.
> 
> Altera specifies the region size
> so that end address matches to the base of the next peripheral.
> This is just a matter of SOCFPGA address mapping.
> 
> In my opinion, the binding document should not be oriented
> to a particular SoC, which is not true for other SoCs.
ok. Thank you for detailed response.
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Masahiro Yamada Sept. 21, 2017, 11:10 a.m. | #6
2017-09-21 15:09 GMT+09:00 Oleksij Rempel <ore@pengutronix.de>:
> Hi,
>
> On 21.09.2017 07:26, Masahiro Yamada wrote:
>>
>> Hi.
>
>
> ......
>
>>> Hm.. according to
>>>
>>> https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
>>> Table 13-18: NAND Controller Module Data Space Address Range
>>>
>>> Module Instance       Start Address        End Address
>>> NAND_DATA             0xFF900000           0xFF9FFFFF
>>>
>>> So <0xff900000 0x100000> seems to be a proper value.
>>>
>>
>> The Alrera's SOCFPGA document describes so.
>> It is up to each SoC vendor how to describe the register space.
>>
>> I am focusing on the Denali IP
>> because this IP is used among several SoCs.
>>
>>
>>
>> You can see the peripheral region map
>> starting at page 1-18 of the document you referred to:
>>
>> Slave ID      Description                  Base Addr      Size
>> ---------------------------------------------------------------
>> L3REGS        L3 interconnect GPV          0xFF800000      1 MB
>> NANDDATA      NAND flash controller data   0xFF900000     64 KB
>> QSPIDATA      Quad SPI flash data          0xFFA00000      1 MB
>>
>> (In the doc, the base is described as 0xFFB900000, but this is
>> apparently a typo.)
>>
>>
>> The rationale of the "End Address 0xFF9FFFFF" of NAND_DATA
>> is the fact that the base address of the next peripheral (QSPIDATA) is
>> 0xFFA00000.
>>
>>
>>
>>
>> One more, if you look at the next page,
>>
>> Slave ID      Description                      Base Addr     Size
>> ---------------------------------------------------------------
>> NANDREGS      NAND flash controller registers   0xFFB80000   64 KB
>> FPGAMGRDATA   FPGA manager configuration data   0xFFB90000    4 KB
>>
>>
>> The size of NAND register space is described as 64KB,
>> but the rationale is just the start of the next peripheral is 0xFFB90000.
>>
>> (0xFFB90000 - 0xFFB80000 = 0x10000 = 64KB)
>>
>>
>>
>> Altera apparently reserved address space just for the purpose
>> of matching the end address to the base address of the next peripheral.
>>
>>
>> That means, this document specifies address region
>> much bigger than the IP actually provides.
>>
>>
>> If you look at page 13-6, there are only two registers
>> in NANDDATA space.
>>
>> Table 13-4: Register Map for Indexed Addressing
>> Control   0x0
>> Data      0x10
>>
>>
>>
>> For NANDREGS, in page 13-106, the following is the last register
>> in the NANDREGS space.
>>
>> lun_status_cmd
>> Offset 0x7A0
>>
>> Obviously, 0x1000 (4KB) is enough for NANDREGS.
>>
>> To conclude this, this binding document was written
>> based on the Altera's SOCFPGA specification.
>>
>> Altera specifies the region size
>> so that end address matches to the base of the next peripheral.
>> This is just a matter of SOCFPGA address mapping.
>>
>> In my opinion, the binding document should not be oriented
>> to a particular SoC, which is not true for other SoCs.
>
> ok. Thank you for detailed response.



BTW, I am not forcing you to change the SOCFPGA DTS.
It is up to you and Dihn whether change it or not.

I do not have any SOCFPGA board.
Rob Herring Sept. 21, 2017, 10:55 p.m. | #7
On Thu, Sep 14, 2017 at 04:17:36PM +0900, Masahiro Yamada wrote:
> This example allocates too much for register regions.  Especially,
> there are only two registers in the "nand_data" interface of this
> hardware (ADDR: 0x00, DATA: 0x10).
> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
> 
>  Documentation/devicetree/bindings/mtd/denali-nand.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Acked-by: Rob Herring <robh@kernel.org>
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Patch

diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt
index 504291d..0ee8edb 100644
--- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt
@@ -29,7 +29,7 @@  nand: nand@ff900000 {
 	#address-cells = <1>;
 	#size-cells = <1>;
 	compatible = "altr,socfpga-denali-nand";
-	reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
+	reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
 	reg-names = "nand_data", "denali_reg";
 	interrupts = <0 144 4>;
 };