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[U-Boot,v4,18/18] x86: minnowmax: Enable USB xHCI support

Message ID 1500472210-15508-19-git-send-email-bmeng.cn@gmail.com
State Accepted
Delegated to: Marek Vasut
Headers show

Commit Message

Bin Meng July 19, 2017, 1:50 p.m. UTC 
BayTrail SoC supports both EHCI and xHCI controllers. However only
one host controller (either EHCI or xHCI) can be used. To enable
HSIC and SS ports, xHCI must be used. This turns on xHCI support on
Intel MinnowMax board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>

---

Changes in v4:
- Rebase on u-boot-usb/master

Changes in v3:
- Rebase on u-boot/master

Changes in v2:
- Drop two x86 patches that were already applied to u-boot-x86

 arch/x86/dts/minnowmax.dts  | 3 +++
 configs/minnowmax_defconfig | 1 +
 2 files changed, 4 insertions(+)
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Patch

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 4c0a8fe..a0ad03c 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -272,6 +272,9 @@ 
 		fsp,enable-spi;
 		fsp,enable-sata;
 		fsp,sata-mode = <SATA_MODE_AHCI>;
+#ifdef CONFIG_USB_XHCI_HCD
+		fsp,enable-xhci;
+#endif
 		fsp,lpe-mode = <LPE_MODE_PCI>;
 		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index a64a0a3..72dea82 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -69,6 +69,7 @@  CONFIG_ICH_SPI=y
 CONFIG_TIMER=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_KEYBOARD=y
 CONFIG_DM_VIDEO=y