| Message ID | 20170605191517.12376-30-sjg@chromium.org |
|---|---|
| State | Superseded |
| Delegated to: | Simon Glass |
| Headers | show |
Hi Simon, On Tue, Jun 6, 2017 at 3:15 AM, Simon Glass <sjg@chromium.org> wrote: > As a demonstration of how to use SCSI with driver model, move link over > to use this. This patch needs more work, but illustrates the concept. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > arch/x86/cpu/ivybridge/sata.c | 38 +++++++++++++++++++++++++++++++++++++- > configs/chromebook_link_defconfig | 2 ++ > 2 files changed, 39 insertions(+), 1 deletion(-) > This is great! Thanks a lot. > diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c > index 0f5e190425..5bbe65d442 100644 > --- a/arch/x86/cpu/ivybridge/sata.c > +++ b/arch/x86/cpu/ivybridge/sata.c > @@ -6,6 +6,7 @@ > */ > > #include <common.h> > +#include <ahci.h> > #include <dm.h> > #include <fdtdec.h> > #include <asm/io.h> > @@ -208,6 +209,20 @@ static void bd82x6x_sata_enable(struct udevice *dev) > dm_pci_write_config16(dev, 0x90, map); > } > > +static int bd82x6x_sata_bind(struct udevice *dev) > +{ > + struct udevice *scsi_dev; > + int ret; > + > + if (gd->flags & GD_FLG_RELOC) { > + ret = ahci_bind_scsi(dev, &scsi_dev); > + if (ret) > + return ret; > + } > + > + return 0; > +} > + > static int bd82x6x_sata_probe(struct udevice *dev) > { > struct udevice *pch; > @@ -219,8 +234,12 @@ static int bd82x6x_sata_probe(struct udevice *dev) > > if (!(gd->flags & GD_FLG_RELOC)) > bd82x6x_sata_enable(dev); > - else > + else { > bd82x6x_sata_init(dev, pch); > + ret = ahci_probe_scsi(dev); > + if (ret) > + return ret; > + } > > return 0; > } > @@ -234,5 +253,22 @@ U_BOOT_DRIVER(ahci_ivybridge_drv) = { > .name = "ahci_ivybridge", > .id = UCLASS_AHCI, > .of_match = bd82x6x_ahci_ids, > + .bind = bd82x6x_sata_bind, > .probe = bd82x6x_sata_probe, > }; > + > +static struct pci_device_id chromebook_ssd_supported[] = { > + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI) }, > + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, > + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE) }, > + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, > + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6) }, > + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, > + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE) }, > + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI) }, > + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, > + PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI) }, > + {}, > +}; Since AHCI is pretty generic, instead of providing device list filter, can we just use PCI class and sub-class for AHCI, like USB? For Ivybridge specific stuff, we can call the low level initialization function as part of the SoC/platform initialization codes. > + > +U_BOOT_PCI_DEVICE(ahci_ivybridge_drv, chromebook_ssd_supported); > diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig > index a463270514..503581dfce 100644 > --- a/configs/chromebook_link_defconfig > +++ b/configs/chromebook_link_defconfig > @@ -40,6 +40,8 @@ CONFIG_OF_CONTROL=y > CONFIG_REGMAP=y > CONFIG_SYSCON=y > CONFIG_SCSI=y > +CONFIG_DM_SCSI=y > +CONFIG_BLK=y > CONFIG_CPU=y > CONFIG_DM_I2C=y > CONFIG_SYS_I2C_INTEL=y > -- Regards, Bin
Hi Bin, On 12 June 2017 at 21:15, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Simon, > > On Tue, Jun 6, 2017 at 3:15 AM, Simon Glass <sjg@chromium.org> wrote: >> As a demonstration of how to use SCSI with driver model, move link over >> to use this. This patch needs more work, but illustrates the concept. >> >> Signed-off-by: Simon Glass <sjg@chromium.org> >> --- >> >> arch/x86/cpu/ivybridge/sata.c | 38 +++++++++++++++++++++++++++++++++++++- >> configs/chromebook_link_defconfig | 2 ++ >> 2 files changed, 39 insertions(+), 1 deletion(-) >> > > This is great! Thanks a lot. > >> diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c >> index 0f5e190425..5bbe65d442 100644 >> --- a/arch/x86/cpu/ivybridge/sata.c >> +++ b/arch/x86/cpu/ivybridge/sata.c >> @@ -6,6 +6,7 @@ >> */ >> >> #include <common.h> >> +#include <ahci.h> >> #include <dm.h> >> #include <fdtdec.h> >> #include <asm/io.h> >> @@ -208,6 +209,20 @@ static void bd82x6x_sata_enable(struct udevice *dev) >> dm_pci_write_config16(dev, 0x90, map); >> } >> >> +static int bd82x6x_sata_bind(struct udevice *dev) >> +{ >> + struct udevice *scsi_dev; >> + int ret; >> + >> + if (gd->flags & GD_FLG_RELOC) { >> + ret = ahci_bind_scsi(dev, &scsi_dev); >> + if (ret) >> + return ret; >> + } >> + >> + return 0; >> +} >> + >> static int bd82x6x_sata_probe(struct udevice *dev) >> { >> struct udevice *pch; >> @@ -219,8 +234,12 @@ static int bd82x6x_sata_probe(struct udevice *dev) >> >> if (!(gd->flags & GD_FLG_RELOC)) >> bd82x6x_sata_enable(dev); >> - else >> + else { >> bd82x6x_sata_init(dev, pch); >> + ret = ahci_probe_scsi(dev); >> + if (ret) >> + return ret; >> + } >> >> return 0; >> } >> @@ -234,5 +253,22 @@ U_BOOT_DRIVER(ahci_ivybridge_drv) = { >> .name = "ahci_ivybridge", >> .id = UCLASS_AHCI, >> .of_match = bd82x6x_ahci_ids, >> + .bind = bd82x6x_sata_bind, >> .probe = bd82x6x_sata_probe, >> }; >> + >> +static struct pci_device_id chromebook_ssd_supported[] = { >> + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI) }, >> + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, >> + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE) }, >> + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, >> + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6) }, >> + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, >> + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE) }, >> + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI) }, >> + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, >> + PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI) }, >> + {}, >> +}; > > Since AHCI is pretty generic, instead of providing device list > filter, can we just use PCI class and sub-class for AHCI, like USB? > > For Ivybridge specific stuff, we can call the low level initialization > function as part of the SoC/platform initialization codes. Actually this code should be dropped. I was experimenting with how to enable it generally (as you suggest). But we really need to do what you say but in a separate file. The question I have is how to enable a sub-class to use this driver, since some devices will want to use ahci.c (i.e. SCSI-based) and some will have their own drivers. I'm not sure that we support finding more specific PCI drivers first. Anyway I will respin this series with this patch updated and we can work it out from there. Regards, Simon
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index 0f5e190425..5bbe65d442 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <ahci.h> #include <dm.h> #include <fdtdec.h> #include <asm/io.h> @@ -208,6 +209,20 @@ static void bd82x6x_sata_enable(struct udevice *dev) dm_pci_write_config16(dev, 0x90, map); } +static int bd82x6x_sata_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + int ret; + + if (gd->flags & GD_FLG_RELOC) { + ret = ahci_bind_scsi(dev, &scsi_dev); + if (ret) + return ret; + } + + return 0; +} + static int bd82x6x_sata_probe(struct udevice *dev) { struct udevice *pch; @@ -219,8 +234,12 @@ static int bd82x6x_sata_probe(struct udevice *dev) if (!(gd->flags & GD_FLG_RELOC)) bd82x6x_sata_enable(dev); - else + else { bd82x6x_sata_init(dev, pch); + ret = ahci_probe_scsi(dev); + if (ret) + return ret; + } return 0; } @@ -234,5 +253,22 @@ U_BOOT_DRIVER(ahci_ivybridge_drv) = { .name = "ahci_ivybridge", .id = UCLASS_AHCI, .of_match = bd82x6x_ahci_ids, + .bind = bd82x6x_sata_bind, .probe = bd82x6x_sata_probe, }; + +static struct pci_device_id chromebook_ssd_supported[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI) }, + {}, +}; + +U_BOOT_PCI_DEVICE(ahci_ivybridge_drv, chromebook_ssd_supported); diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig index a463270514..503581dfce 100644 --- a/configs/chromebook_link_defconfig +++ b/configs/chromebook_link_defconfig @@ -40,6 +40,8 @@ CONFIG_OF_CONTROL=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_BLK=y CONFIG_CPU=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_INTEL=y
As a demonstration of how to use SCSI with driver model, move link over to use this. This patch needs more work, but illustrates the concept. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/x86/cpu/ivybridge/sata.c | 38 +++++++++++++++++++++++++++++++++++++- configs/chromebook_link_defconfig | 2 ++ 2 files changed, 39 insertions(+), 1 deletion(-)