| Message ID | 1491384774-49629-16-git-send-email-ley.foon.tan@intel.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
On Wed, Apr 5, 2017 at 4:32 AM, Ley Foon Tan <ley.foon.tan@intel.com> wrote: > These registers only available for Gen5 device, exclude them > from Arria 10 build. > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> > --- > drivers/fpga/socfpga.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c > index f1b2f2c..3751574 100644 > --- a/drivers/fpga/socfpga.c > +++ b/drivers/fpga/socfpga.c > @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; > > static struct socfpga_fpga_manager *fpgamgr_regs = > (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > static struct socfpga_system_manager *sysmgr_regs = > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > +#endif The ordering of the patches is important. You shouldn't need this patch because in patch #17, you wrapped the CONFIG_FPGA_SOCFPGA define by a GEN5 build. So this shouldn't get compiled at all. But then I had a comment as to why the need to remove the FPGA build for A10. Dinh
On Fri, Apr 7, 2017 at 10:26 PM, Dinh Nguyen <dinh.linux@gmail.com> wrote: > On Wed, Apr 5, 2017 at 4:32 AM, Ley Foon Tan <ley.foon.tan@intel.com> wrote: >> These registers only available for Gen5 device, exclude them >> from Arria 10 build. >> >> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> >> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> >> --- >> drivers/fpga/socfpga.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c >> index f1b2f2c..3751574 100644 >> --- a/drivers/fpga/socfpga.c >> +++ b/drivers/fpga/socfpga.c >> @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; >> >> static struct socfpga_fpga_manager *fpgamgr_regs = >> (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; >> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) >> static struct socfpga_system_manager *sysmgr_regs = >> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; >> +#endif > > The ordering of the patches is important. You shouldn't need this patch > because in patch #17, you wrapped the CONFIG_FPGA_SOCFPGA > define by a GEN5 build. So this shouldn't get compiled at all. > > But then I had a comment as to why the need to remove the FPGA build > for A10. > Yes, we can remove this patch since CONFIG_FPGA_SOCFPGA is not enable for A10. As explained in another comment, A10 FPGA support will be in coming patch. Not including in this patch series. Thanks. Regards Ley Foon
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index f1b2f2c..3751574 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif /* Set CD ratio */ static void fpgamgr_set_cd_ratio(unsigned long ratio) @@ -268,8 +270,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Prior programming the FPGA, all bridges need to be shut off */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Disable all signals from hps peripheral controller to fpga */ writel(0, &sysmgr_regs->fpgaintfgrp_module); +#endif /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 @@ -278,8 +282,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(1); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Unmap the bridges from NIC-301 */ writel(0x1, SOCFPGA_L3REGS_ADDRESS); +#endif /* Initialize the FPGA Manager */ status = fpgamgr_program_init();