From patchwork Wed Apr 5 09:32:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ley Foon Tan X-Patchwork-Id: 747197 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vyh3351ZTz9s7t for ; Wed, 5 Apr 2017 19:52:31 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="key not found in DNS" (0-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NXRwBmZh"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id 520E1C21C4E; Wed, 5 Apr 2017 09:45:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 494C9C21C86; Wed, 5 Apr 2017 09:34:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 61EE5C21C89; Wed, 5 Apr 2017 09:34:23 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lists.denx.de (Postfix) with ESMTPS id 279C6C21C89 for ; Wed, 5 Apr 2017 09:33:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491384839; x=1522920839; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=qxhfOukJCviuN11Qxnpjf0wdwOXU7QuSf2yMaAdEYmk=; b=NXRwBmZhiyjgoCWurCRufKbuHT046PqtO7zv+vsJAXFwYDQ8G6pBqOMP 6CM+GBBLhb6Ig2EL8dR0u7rPa4/QMA==; Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Apr 2017 02:33:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.36,278,1486454400"; d="scan'208"; a="1131270798" Received: from unknown (HELO ubuntu) ([10.226.248.159]) by fmsmga001.fm.intel.com with SMTP; 05 Apr 2017 02:33:54 -0700 Received: by ubuntu (sSMTP sendmail emulation); Wed, 05 Apr 2017 17:33:53 +0800 From: Ley Foon Tan To: u-boot@lists.denx.de, Marek Vasut Date: Wed, 5 Apr 2017 17:32:50 +0800 Message-Id: <1491384774-49629-16-git-send-email-ley.foon.tan@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491384774-49629-1-git-send-email-ley.foon.tan@intel.com> References: <1491384774-49629-1-git-send-email-ley.foon.tan@intel.com> Cc: Tien Fong Chee , Chin Liang See Subject: [U-Boot] [PATCH v4 15/19] drivers: fpga: Add compile switch for Gen5 only registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" These registers only available for Gen5 device, exclude them from Arria 10 build. Signed-off-by: Tien Fong Chee Signed-off-by: Ley Foon Tan --- drivers/fpga/socfpga.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c index f1b2f2c..3751574 100644 --- a/drivers/fpga/socfpga.c +++ b/drivers/fpga/socfpga.c @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; +#endif /* Set CD ratio */ static void fpgamgr_set_cd_ratio(unsigned long ratio) @@ -268,8 +270,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Prior programming the FPGA, all bridges need to be shut off */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Disable all signals from hps peripheral controller to fpga */ writel(0, &sysmgr_regs->fpgaintfgrp_module); +#endif /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 @@ -278,8 +282,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(1); +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* Unmap the bridges from NIC-301 */ writel(0x1, SOCFPGA_L3REGS_ADDRESS); +#endif /* Initialize the FPGA Manager */ status = fpgamgr_program_init();