diff mbox

[U-Boot,31/82] x86: ivybridge: Fix PCH power setup

Message ID 1474860866-16406-32-git-send-email-sjg@chromium.org
State Accepted
Commit 4e0318c32f01e5178f9ddd29313fcb24a1584dd6
Delegated to: Bin Meng
Headers show

Commit Message

Simon Glass Sept. 26, 2016, 3:33 a.m. UTC
At present pch_power_options() has the arguments to writel() around the
wrong way. Fix this and update it to compile on 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/ivybridge/lpc.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Bin Meng Oct. 11, 2016, 3:16 a.m. UTC | #1
On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass <sjg@chromium.org> wrote:
> At present pch_power_options() has the arguments to writel() around the
> wrong way. Fix this and update it to compile on 64-bit machines.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/ivybridge/lpc.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng Oct. 11, 2016, 3:42 a.m. UTC | #2
On Tue, Oct 11, 2016 at 11:16 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Sep 26, 2016 at 11:33 AM, Simon Glass <sjg@chromium.org> wrote:
>> At present pch_power_options() has the arguments to writel() around the
>> wrong way. Fix this and update it to compile on 64-bit machines.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>>  arch/x86/cpu/ivybridge/lpc.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!
diff mbox

Patch

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 0b4343a..c564713 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -215,10 +215,10 @@  static int pch_power_options(struct udevice *pch)
 	dm_pci_read_config16(pch, 0x40, &pmbase);
 	pmbase &= 0xfffe;
 
-	writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
-						"intel,gpe0-enable", 0));
-	writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
-						"intel,alt-gp-smi-enable", 0));
+	writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0),
+	       (ulong)pmbase + GPE0_EN);
+	writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0),
+	       (ulong)pmbase + ALT_GP_SMI_EN);
 
 	/* Set up power management block and determine sleep mode */
 	reg32 = inl(pmbase + 0x04); /* PM1_CNT */