| Message ID | 5785DDB4.80102@denx.de |
|---|---|
| State | RFC |
| Delegated to: | Bin Meng |
| Headers | show |
Hi, On 13 July 2016 at 00:20, Stefan Roese <sr@denx.de> wrote: > Hi! > > I'm currently trying to get xHCI working on some BayTrail based > x86 boards. For this I've added DM support to xhci-pci and made a > small change to cache.h to enable compilation of the xhci driver on > x86 (please find those 2 patches attached - I'll send then to the > list once this is resolved). But I noticed that the xhci driver > hangs in xhci_queue_command() in this line: > > xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST); > > when first writing to the doorbell register. Reading from this doorbell > register still works just fine. > > IIRC, Simon has mentioned that xHCI still has some "issues" on x86. > Simon, is this what you have seen as well? Does anyone have some ideas > how to solve this? I'm really not sure what is wrong, sorry. The discussion about enabling the pin settings correctly may be relevant since I believe two GPIOs need to be set up for both ports to work, and that patch was never cleaned up and applied, so far as I know... Regards, Simon
Hi Simon, On 15.07.2016 05:19, Simon Glass wrote: > On 13 July 2016 at 00:20, Stefan Roese <sr@denx.de> wrote: >> Hi! >> >> I'm currently trying to get xHCI working on some BayTrail based >> x86 boards. For this I've added DM support to xhci-pci and made a >> small change to cache.h to enable compilation of the xhci driver on >> x86 (please find those 2 patches attached - I'll send then to the >> list once this is resolved). But I noticed that the xhci driver >> hangs in xhci_queue_command() in this line: >> >> xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST); >> >> when first writing to the doorbell register. Reading from this doorbell >> register still works just fine. >> >> IIRC, Simon has mentioned that xHCI still has some "issues" on x86. >> Simon, is this what you have seen as well? Does anyone have some ideas >> how to solve this? > > I'm really not sure what is wrong, sorry. The discussion about > enabling the pin settings correctly may be relevant since I believe > two GPIOs need to be set up for both ports to work, and that patch was > never cleaned up and applied, so far as I know... I see. I my case, it's not related to the GPIO issue - as the ports are not enabled via GPIO on the Congatec board where I'm currently testing on. I've updated the xHCI PCI support a bit (no hangup any more, but still not working correctly) and will post the current version as WIP today, as I need to switch to some other tasks for a while. Perhaps someone else is interested in xHCI on x86 enough to take a look at it in the meantime... Thanks, Stefan
From 73e74da69cc2606eb2815bd97f8c2dff3c17c6a7 Mon Sep 17 00:00:00 2001 From: Stefan Roese <sr@denx.de> Date: Wed, 6 Jul 2016 08:27:19 +0200 Subject: [PATCH] WIP: usb: xhci-pci: Add DM support This patch adds DM support to the xHCI PCI driver. Enabling its use e.g. in x86 platforms. Signed-off-by: Stefan Roese <sr@denx.de> --- drivers/usb/host/xhci-pci.c | 76 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c index 361fcce..cf22047 100644 --- a/drivers/usb/host/xhci-pci.c +++ b/drivers/usb/host/xhci-pci.c @@ -7,12 +7,15 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <pci.h> #include <usb.h> #include "xhci.h" +#ifndef CONFIG_DM_USB + /* * Create the appropriate control structures to manage a new XHCI host * controller. @@ -58,3 +61,76 @@ int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, void xhci_hcd_stop(int index) { } + +#else + +static void xhci_pci_init(struct udevice *dev, struct xhci_hccr **ret_hccr, + struct xhci_hcor **ret_hcor) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + u32 cmd; + + hccr = (struct xhci_hccr *)dm_pci_map_bar(dev, + PCI_BASE_ADDRESS_0, PCI_REGION_MEM); + hcor = (struct xhci_hcor *)((uintptr_t) hccr + + HC_LENGTH(xhci_readl(&hccr->cr_capbase))); + + debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); + + *ret_hccr = hccr; + *ret_hcor = hcor; + + /* enable busmaster */ + dm_pci_read_config32(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + dm_pci_write_config32(dev, PCI_COMMAND, cmd); +} + +static int xhci_pci_probe(struct udevice *dev) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + + xhci_pci_init(dev, &hccr, &hcor); + + return xhci_register(dev, hccr, hcor); +} + +static int xhci_pci_remove(struct udevice *dev) +{ + int ret; + + ret = xhci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id xhci_pci_ids[] = { + { .compatible = "xhci-pci" }, + { } +}; + +U_BOOT_DRIVER(xhci_pci) = { + .name = "xhci_pci", + .id = UCLASS_USB, + .probe = xhci_pci_probe, + .remove = xhci_pci_remove, + .of_match = xhci_pci_ids, + .ops = &xhci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +static struct pci_device_id xhci_pci_supported[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0) }, + {}, +}; + +U_BOOT_PCI_DEVICE(xhci_pci, xhci_pci_supported); + +#endif /* CONFIG_DM_USB */ -- 2.9.0