| Message ID | 1454319658-17431-11-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Accepted |
| Commit | 79d4eb627cffbc3ab7cefdd623fa39fefaaedbe7 |
| Delegated to: | Bin Meng |
| Headers | show |
On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote: > On some newer chipset (eg: BayTrail), there is an IO base address > register on the PCH device which configures the base address of a > memory-mapped I/O controller. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > drivers/pch/pch-uclass.c | 11 +++++++++++ > include/pch.h | 18 ++++++++++++++++++ > 2 files changed, 29 insertions(+) Reviewed-by: Simon Glass <sjg@chromium.org> Tested on Minnowmax: Tested-by: Simon Glass <sjg@chromium.org>
On Tue, Feb 2, 2016 at 12:19 AM, Simon Glass <sjg@chromium.org> wrote: > On 1 February 2016 at 02:40, Bin Meng <bmeng.cn@gmail.com> wrote: >> On some newer chipset (eg: BayTrail), there is an IO base address >> register on the PCH device which configures the base address of a >> memory-mapped I/O controller. >> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >> --- >> >> drivers/pch/pch-uclass.c | 11 +++++++++++ >> include/pch.h | 18 ++++++++++++++++++ >> 2 files changed, 29 insertions(+) > > Reviewed-by: Simon Glass <sjg@chromium.org> > Tested on Minnowmax: > Tested-by: Simon Glass <sjg@chromium.org> applied to u-boot-x86/master, thanks!
diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c index 48a3965..7216660 100644 --- a/drivers/pch/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -44,6 +44,17 @@ int pch_get_gpio_base(struct udevice *dev, u32 *gbasep) return ops->get_gpio_base(dev, gbasep); } +int pch_get_io_base(struct udevice *dev, u32 *iobasep) +{ + struct pch_ops *ops = pch_get_ops(dev); + + *iobasep = 0; + if (!ops->get_io_base) + return -ENOSYS; + + return ops->get_io_base(dev, iobasep); +} + static int pch_uclass_post_bind(struct udevice *bus) { /* diff --git a/include/pch.h b/include/pch.h index b378865..222e908 100644 --- a/include/pch.h +++ b/include/pch.h @@ -41,6 +41,15 @@ struct pch_ops { * @return 0 if OK, -ve on error (e.g. there is no GPIO base) */ int (*get_gpio_base)(struct udevice *dev, u32 *gbasep); + + /** + * get_io_base() - get the address of IO base + * + * @dev: PCH device to check + * @iobasep: Returns address of IO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no IO base) + */ + int (*get_io_base)(struct udevice *dev, u32 *iobasep); }; #define pch_get_ops(dev) ((struct pch_ops *)(dev)->driver->ops) @@ -73,4 +82,13 @@ int pch_set_spi_protect(struct udevice *dev, bool protect); */ int pch_get_gpio_base(struct udevice *dev, u32 *gbasep); +/** + * pch_get_io_base() - get the address of IO base + * + * @dev: PCH device to check + * @iobasep: Returns address of IO base if available, else 0 + * @return 0 if OK, -ve on error (e.g. there is no IO base) + */ +int pch_get_io_base(struct udevice *dev, u32 *iobasep); + #endif
On some newer chipset (eg: BayTrail), there is an IO base address register on the PCH device which configures the base address of a memory-mapped I/O controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- drivers/pch/pch-uclass.c | 11 +++++++++++ include/pch.h | 18 ++++++++++++++++++ 2 files changed, 29 insertions(+)