| Message ID | 1438939726-4781-4-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Simon Glass |
| Headers | show |
On Fri, Aug 07, 2015 at 02:28:46AM -0700, Bin Meng wrote: > Intel FSP has the capability to walk through the microcode blocks > which are passed as the TempRamInit() parameter from U-Boot and > finds the most appropriate microcode which is suitable for the cpu > on which it is running. Now we've seen several steppings for Intel > BayTrail series processors, adding those microcodes to the Intel > BayleyBay and MinnowMax board device tree files. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> With my Minnowboard Max that doesn't work in mainline right now due to newer stepping and thus needing newer microcode: Tested-by: Tom Rini <trini@konsulko.com>
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index ea27537..bceef60 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -235,6 +235,8 @@ data = < #include "microcode/m0230671117.dtsi" +#include "microcode/m0130673322.dtsi" +#include "microcode/m0130679901.dtsi" >; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 5711510..2af67e4 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -198,6 +198,7 @@ data = < #include "microcode/m0130673322.dtsi" +#include "microcode/m0130679901.dtsi" >; }; };
Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/dts/bayleybay.dts | 2 ++ arch/x86/dts/minnowmax.dts | 1 + 2 files changed, 3 insertions(+)