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[U-Boot,06/11] x86: queensbay: Change CPU_ADDR_BITS to 32

Message ID BLU437-SMTP34C8BC4B0BB8BE3DE19AD4BFA80@phx.gbl
State Superseded
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng July 1, 2015, 8:28 a.m. UTC 
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/cpu/queensbay/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Simon Glass July 1, 2015, 2:59 p.m. UTC | #1 
On 1 July 2015 at 02:28, Bin Meng <bmeng.cn@gmail.com> wrote:
> Per CPUID:80000008h result, the maximum physical address bits of
> TunnelCreek processor is 32 instead of default 36. This will fix
> the incorrect decoding of MTRR range mask.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/cpu/queensbay/Kconfig | 4 ++++
>  1 file changed, 4 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>
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Patch

diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 397e599..fbf85f2 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -38,4 +38,8 @@  config CMC_ADDR
 	  The default base address of 0xfffb0000 indicates that the binary must
 	  be located at offset 0xb0000 from the beginning of a 1MB flash device.
 
+config CPU_ADDR_BITS
+	int
+	default 32
+
 endif