| Message ID | BLU437-SMTP73DD77760B3DE68BEEE830BFA00@phx.gbl |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
On 22 June 2015 at 22:18, Bin Meng <bmeng.cn@gmail.com> wrote: > I/O APIC registers are addressed indirectly. Add io_apic_read() and > io_apic_write() routines to help register access. Two macros for I/O > APIC ID and version register offset are also added. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > > --- > > Changes in v2: > - Do not use inline for register access > > arch/x86/cpu/Makefile | 2 +- > arch/x86/cpu/ioapic.c | 21 +++++++++++++++++++++ > arch/x86/include/asm/ioapic.h | 24 ++++++++++++++++++++++++ > 3 files changed, 46 insertions(+), 1 deletion(-) > create mode 100644 arch/x86/cpu/ioapic.c Acked-by: Simon Glass <sjg@chromium.org>
On 23 June 2015 at 19:45, Simon Glass <sjg@chromium.org> wrote: > On 22 June 2015 at 22:18, Bin Meng <bmeng.cn@gmail.com> wrote: >> I/O APIC registers are addressed indirectly. Add io_apic_read() and >> io_apic_write() routines to help register access. Two macros for I/O >> APIC ID and version register offset are also added. >> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >> >> --- >> >> Changes in v2: >> - Do not use inline for register access >> >> arch/x86/cpu/Makefile | 2 +- >> arch/x86/cpu/ioapic.c | 21 +++++++++++++++++++++ >> arch/x86/include/asm/ioapic.h | 24 ++++++++++++++++++++++++ >> 3 files changed, 46 insertions(+), 1 deletion(-) >> create mode 100644 arch/x86/cpu/ioapic.c > > Acked-by: Simon Glass <sjg@chromium.org> Applied to u-boot-x86, thanks!
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 48197fb..8a8e63e 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -19,7 +19,7 @@ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ -obj-y += irq.o lapic.o +obj-y += irq.o lapic.o ioapic.o obj-$(CONFIG_SMP) += mp_init.o obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c new file mode 100644 index 0000000..112a9c6 --- /dev/null +++ b/arch/x86/cpu/ioapic.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/ioapic.h> + +u32 io_apic_read(u32 reg) +{ + writel(reg, IO_APIC_INDEX); + return readl(IO_APIC_DATA); +} + +void io_apic_write(u32 reg, u32 val) +{ + writel(reg, IO_APIC_INDEX); + writel(val, IO_APIC_DATA); +} diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h index f5d69db..77c443e 100644 --- a/arch/x86/include/asm/ioapic.h +++ b/arch/x86/include/asm/ioapic.h @@ -15,4 +15,28 @@ #define IO_APIC_INDEX (IO_APIC_ADDR + 0x00) #define IO_APIC_DATA (IO_APIC_ADDR + 0x10) +/* Indirect addressed register offset */ +#define IO_APIC_ID 0x00 +#define IO_APIC_VER 0x01 + +/** + * io_apic_read() - Read I/O APIC register + * + * This routine reads I/O APIC indirect addressed register. + * + * @reg: address of indirect addressed register + * @return: register value to read + */ +u32 io_apic_read(u32 reg); + +/** + * io_apic_write() - Write I/O APIC register + * + * This routine writes I/O APIC indirect addressed register. + * + * @reg: address of indirect addressed register + * @val: register value to write + */ +void io_apic_write(u32 reg, u32 val); + #endif
I/O APIC registers are addressed indirectly. Add io_apic_read() and io_apic_write() routines to help register access. Two macros for I/O APIC ID and version register offset are also added. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v2: - Do not use inline for register access arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/ioapic.c | 21 +++++++++++++++++++++ arch/x86/include/asm/ioapic.h | 24 ++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 arch/x86/cpu/ioapic.c