| Message ID | BLU437-SMTP45DE75C90E4998E3505FC0BFA60@phx.gbl |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
On 16 June 2015 at 21:15, Bin Meng <bmeng.cn@gmail.com> wrote: > Intel Crown Bay board has a TunnelCreek processor which supports > hyper-threading. Add /cpus node in the crownbay.dts and enable > the MP initialization. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > Acked-by: Simon Glass <sjg@chromium.org> > > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: > - Move CONFIG_MAX_CPUS after CONFIG_SMP in crownbay_defconfig to > match the order in Kconfig > > arch/x86/dts/crownbay.dts | 20 ++++++++++++++++++++ > configs/crownbay_defconfig | 4 ++++ > 2 files changed, 24 insertions(+) Applied to u-boot-x86, thanks!
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index d68efda..1ec90cd 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -23,6 +23,26 @@ silent_console = <0>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <1>; + }; + + }; + gpioa { compatible = "intel,ich6-gpio"; u-boot,dm-pre-reloc; diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index d3a370d..d21177d 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -2,6 +2,10 @@ CONFIG_X86=y CONFIG_VENDOR_INTEL=y CONFIG_DEFAULT_DEVICE_TREE="crownbay" CONFIG_TARGET_CROWNBAY=y +CONFIG_SMP=y +CONFIG_MAX_CPUS=2 CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_CMD_CPU=y CONFIG_CMD_NET=y CONFIG_OF_CONTROL=y +CONFIG_CPU=y