| Message ID | 1428479031-26597-1-git-send-email-igal.liberman@freescale.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Wed, 2015-04-08 at 10:43 +0300, Igal.Liberman wrote: > @@ -76,6 +77,52 @@ Required properties: > > Recommended properties: > - clocks: Should be the phandle of input parent clock > + For "fsl,fman-clk-mux" clock there are several options for parent > + clock (clock provider), the parent is determined according to the > + Reset Configuration Word of the specific device: > + * P2041, P3041: > + * 0 - equal to platform PLL divided by 2 > + * 1 - equal to PLL2 divided by 2 > + * P4080 (Both FMans): > + * 0 - equal to platform PLL divided by 2 > + * 1 - equal to PLL3 divided by 2 ... Again, the clock specifier format is determined by the clock provider, not the clock consumer. -Scott
Regards, Igal Liberman. > -----Original Message----- > From: Wood Scott-B07421 > Sent: Thursday, April 09, 2015 12:12 AM > To: Liberman Igal-B31950 > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > Subject: Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > On Wed, 2015-04-08 at 10:43 +0300, Igal.Liberman wrote: > > @@ -76,6 +77,52 @@ Required properties: > > > > Recommended properties: > > - clocks: Should be the phandle of input parent clock > > + For "fsl,fman-clk-mux" clock there are several options for parent > > + clock (clock provider), the parent is determined according to the > > + Reset Configuration Word of the specific device: > > + * P2041, P3041: > > + * 0 - equal to platform PLL divided by 2 > > + * 1 - equal to PLL2 divided by 2 > > + * P4080 (Both FMans): > > + * 0 - equal to platform PLL divided by 2 > > + * 1 - equal to PLL3 divided by 2 > ... > > > Again, the clock specifier format is determined by the clock provider, not the > clock consumer. > Scott, The "clocks" property contains all possible clock providers, right? In the text above I'm trying to explain how the FMan clock provider is determined and what are the options for each SoC. Do you think that we shouldn't have this explanation? Can you please elaborate? Igal. > -Scott >
On Thu, 2015-04-09 at 02:18 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Thursday, April 09, 2015 12:12 AM > > To: Liberman Igal-B31950 > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > Subject: Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Wed, 2015-04-08 at 10:43 +0300, Igal.Liberman wrote: > > > @@ -76,6 +77,52 @@ Required properties: > > > > > > Recommended properties: > > > - clocks: Should be the phandle of input parent clock > > > + For "fsl,fman-clk-mux" clock there are several options for parent > > > + clock (clock provider), the parent is determined according to the > > > + Reset Configuration Word of the specific device: > > > + * P2041, P3041: > > > + * 0 - equal to platform PLL divided by 2 > > > + * 1 - equal to PLL2 divided by 2 > > > + * P4080 (Both FMans): > > > + * 0 - equal to platform PLL divided by 2 > > > + * 1 - equal to PLL3 divided by 2 > > ... > > > > > > Again, the clock specifier format is determined by the clock provider, not the > > clock consumer. > > > > Scott, > The "clocks" property contains all possible clock providers, right? > In the text above I'm trying to explain how the FMan clock provider is determined and what are the options for each SoC. > Do you think that we shouldn't have this explanation? Can you please elaborate? I'm saying that the clock specifiers must be the same regardless of the node that is consuming the clock. You can't define certain values as only being "for fsl,fman-clk-mux". -Scott
Regards, Igal Liberman. > -----Original Message----- > From: Wood Scott-B07421 > Sent: Thursday, April 09, 2015 8:03 PM > To: Liberman Igal-B31950 > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > Subject: Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > On Thu, 2015-04-09 at 02:18 -0500, Liberman Igal-B31950 wrote: > > > > > > Regards, > > Igal Liberman. > > > > > -----Original Message----- > > > From: Wood Scott-B07421 > > > Sent: Thursday, April 09, 2015 12:12 AM > > > To: Liberman Igal-B31950 > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > Subject: Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan > > > clock mux > > > > > > On Wed, 2015-04-08 at 10:43 +0300, Igal.Liberman wrote: > > > > @@ -76,6 +77,52 @@ Required properties: > > > > > > > > Recommended properties: > > > > - clocks: Should be the phandle of input parent clock > > > > + For "fsl,fman-clk-mux" clock there are several options for parent > > > > + clock (clock provider), the parent is determined according to the > > > > + Reset Configuration Word of the specific device: > > > > + * P2041, P3041: > > > > + * 0 - equal to platform PLL divided by 2 > > > > + * 1 - equal to PLL2 divided by 2 > > > > + * P4080 (Both FMans): > > > > + * 0 - equal to platform PLL divided by 2 > > > > + * 1 - equal to PLL3 divided by 2 > > > ... > > > > > > > > > Again, the clock specifier format is determined by the clock > > > provider, not the clock consumer. > > > > > > > Scott, > > The "clocks" property contains all possible clock providers, right? > > In the text above I'm trying to explain how the FMan clock provider is > determined and what are the options for each SoC. > > Do you think that we shouldn't have this explanation? Can you please > elaborate? > > I'm saying that the clock specifiers must be the same regardless of the node > that is consuming the clock. You can't define certain values as only being "for > fsl,fman-clk-mux". > Just to make things clear, In "fm0clk/fm1clk" node, "clocks" holds a list of clock specifiers. This list reflects all optional clock providers for a specific hardware, this list varies between different SoCs. All those possible providers described by other nodes, as clock providers. Please notice that this bindings describes the possible source clock for FMan mux, not the providers themselves. You mentioned the following: "You can't define certain values as only being "for fsl,fman-clk-mux"." I'm defining those values in the clock provider nodes and using those values as clock providers for FMan mux, it can be used be other HW blocks too. Igal. > -Scott >
On Sun, 2015-04-12 at 10:54 -0500, Liberman Igal-B31950 wrote: > > > Regards, > Igal Liberman. > > > -----Original Message----- > > From: Wood Scott-B07421 > > Sent: Thursday, April 09, 2015 8:03 PM > > To: Liberman Igal-B31950 > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > Subject: Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan clock mux > > > > On Thu, 2015-04-09 at 02:18 -0500, Liberman Igal-B31950 wrote: > > > > > > > > > Regards, > > > Igal Liberman. > > > > > > > -----Original Message----- > > > > From: Wood Scott-B07421 > > > > Sent: Thursday, April 09, 2015 12:12 AM > > > > To: Liberman Igal-B31950 > > > > Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org > > > > Subject: Re: [v2] dt/bindings: qoriq-clock: Add binding for FMan > > > > clock mux > > > > > > > > On Wed, 2015-04-08 at 10:43 +0300, Igal.Liberman wrote: > > > > > @@ -76,6 +77,52 @@ Required properties: > > > > > > > > > > Recommended properties: > > > > > - clocks: Should be the phandle of input parent clock > > > > > + For "fsl,fman-clk-mux" clock there are several options for parent > > > > > + clock (clock provider), the parent is determined according to the > > > > > + Reset Configuration Word of the specific device: > > > > > + * P2041, P3041: > > > > > + * 0 - equal to platform PLL divided by 2 > > > > > + * 1 - equal to PLL2 divided by 2 > > > > > + * P4080 (Both FMans): > > > > > + * 0 - equal to platform PLL divided by 2 > > > > > + * 1 - equal to PLL3 divided by 2 > > > > ... > > > > > > > > > > > > Again, the clock specifier format is determined by the clock > > > > provider, not the clock consumer. > > > > > > > > > > Scott, > > > The "clocks" property contains all possible clock providers, right? > > > In the text above I'm trying to explain how the FMan clock provider is > > determined and what are the options for each SoC. > > > Do you think that we shouldn't have this explanation? Can you please > > elaborate? > > > > I'm saying that the clock specifiers must be the same regardless of the node > > that is consuming the clock. You can't define certain values as only being "for > > fsl,fman-clk-mux". > > > > Just to make things clear, > In "fm0clk/fm1clk" node, "clocks" holds a list of clock specifiers. > This list reflects all optional clock providers for a specific hardware, this list varies between different SoCs. > All those possible providers described by other nodes, as clock providers. > Please notice that this bindings describes the possible source clock for FMan mux, not the providers themselves. > > You mentioned the following: "You can't define certain values as only being "for fsl,fman-clk-mux"." > I'm defining those values in the clock provider nodes and using those values as clock providers for FMan mux, it can be used be other HW blocks too. My point is that the encoding of the clock specifier is not fman-specific and thus fman should not appear in the description. -Scott
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index df4a259..4d63ac6 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -65,9 +65,10 @@ Required properties: It takes parent's clock-frequency as its clock. * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) + * "fsl,fman-clk-mux" for the Frame Manager clock. - #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" and + "fsl,fman-clk-mux" clocks or <1> for "fsl,qoriq-core-pll-[1,2].0". For "fsl,qoriq-core-pll-[1,2].0" clocks, the single clock-specifier cell may take the following values: * 0 - equal to the PLL frequency @@ -76,6 +77,52 @@ Required properties: Recommended properties: - clocks: Should be the phandle of input parent clock + For "fsl,fman-clk-mux" clock there are several options for parent + clock (clock provider), the parent is determined according to the + Reset Configuration Word of the specific device: + * P2041, P3041: + * 0 - equal to platform PLL divided by 2 + * 1 - equal to PLL2 divided by 2 + * P4080 (Both FMans): + * 0 - equal to platform PLL divided by 2 + * 1 - equal to PLL3 divided by 2 + * P5020: + * 0 - equal to platform PLL divided by 2 + * 1 - equal to PLL2 divided by 2 + * 2 - equal to PLL2 divided by 4 + * P5040 (Both FMans): + * 0 - equal to platform PLL divided by 2 + * 1 - equal to PLL3 divided by 2 + * 2 - equal to PLL3 divided by 4 + * T1024: + * 0 - equal to PLL1 divided by 2 + * T1040: + * 0 - equal to platform PLL + * T2080, B4860, B4420: + * 0 - equal to PLL1 + * 1 - equal to PLL1 divided by 2 + * 2 - equal to PLL1 divided by 3 + * 3 - equal to PLL1 divided by 4 + * 4 - equal to platform PLL + * 5 - equal to PLL2 divided by 2 + * 6 - equal to PLL2 divided by 3 + * T4240: + * FM1: + * 0 equal to PLL1 divided by 2 + * 1 equal to PLL1 divided by 3 + * 2 equal to PLL1 divided by 4 + * 3 equal to platform PLL + * 4 equal to PLL2 divided by 2 + * FM2: + * 0 equal to PLL2 divided by 2 + * 1 equal to PLL2 divided by 3 + * 2 equal to PLL2 divided by 4 + * 3 equal to platform PLL + * 4 equal to PLL1 divided by 2 + * 5 equal to PLL1 divided by 3 + In Part of FMan V3 devices (B4, T2, T4) the single + clock-specifier cell may be determined by the CLKCGxHWACSR + register in addtion to RCW. - clock-names: From common clock binding, indicates the clock name - clock-output-names: From common clock binding, indicates the names of output clocks @@ -139,6 +186,18 @@ Example for clock block and clock provider: clocks = <&sysclk>; clock-output-names = "platform-pll", "platform-pll-div2"; }; + + fm0clk: fm0-clk-mux { + #clock-cells = <0>; + reg = <0x10 4> + compatible = "fsl,fman-clk-mux"; + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>, <&pll0 3>, + <&platform_pll 0>, <&pll1 1>, <&pll1 2>; + clock-names = "pll0", "pll0-div2", "pll0-div3", + "pll0-div4", "platform-pll", "pll1-div2", + "pll1-div3"; + clock-output-names = "fm0-clk"; + }; }; };