diff mbox

[U-Boot,2/6] x86: galileo: Add GPIO support

Message ID 1423038374-2530-3-git-send-email-bmeng.cn@gmail.com
State Accepted
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng Feb. 4, 2015, 8:26 a.m. UTC 
Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
which is just the same one found in other x86 chipset. Since we
programmed the GPIO register block base address, we should be
able to enable the GPIO support on Intel Galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/x86/dts/galileo.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Simon Glass Feb. 5, 2015, 3:26 a.m. UTC | #1 
On 4 February 2015 at 01:26, Bin Meng <bmeng.cn@gmail.com> wrote:
> Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
> which is just the same one found in other x86 chipset. Since we
> programmed the GPIO register block base address, we should be
> able to enable the GPIO support on Intel Galileo board.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  arch/x86/dts/galileo.dts | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass Feb. 6, 2015, 8:27 p.m. UTC | #2 
On 4 February 2015 at 20:26, Simon Glass <sjg@chromium.org> wrote:
> On 4 February 2015 at 01:26, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31),
>> which is just the same one found in other x86 chipset. Since we
>> programmed the GPIO register block base address, we should be
>> able to enable the GPIO support on Intel Galileo board.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>>  arch/x86/dts/galileo.dts | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-x86, thanks!
diff mbox

Patch

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index d462221..2f60aeb 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -65,4 +65,18 @@ 
 		};
 	};
 
+	gpioa {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0 0x20>;
+		bank-name = "A";
+	};
+
+	gpiob {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0x20 0x20>;
+		bank-name = "B";
+	};
+
 };