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[U-Boot,23/25] x86: crownbay: Enable Intel E1000 NIC support

Message ID 1417705431-19772-1-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng Dec. 4, 2014, 3:03 p.m. UTC
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
 board/intel/crownbay/crownbay.c | 6 ++++++
 include/configs/crownbay.h      | 1 +
 2 files changed, 7 insertions(+)

Comments

Simon Glass Dec. 4, 2014, 11:59 p.m. UTC | #1
On 4 December 2014 at 08:03, Bin Meng <bmeng.cn@gmail.com> wrote:
> We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
> controller for now, so enable the Intle E1000 NIC support, which
> can be plugged into any PCIe slot on the Crown Bay board.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  board/intel/crownbay/crownbay.c | 6 ++++++
>  include/configs/crownbay.h      | 1 +
>  2 files changed, 7 insertions(+)

Acked-by: Simon Glass <sjg@chromium.org>
diff mbox

Patch

diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index bbd2596..d2d74a5 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -6,6 +6,7 @@ 
 
 #include <common.h>
 #include <asm/pnp_def.h>
+#include <netdev.h>
 #include <smsc_lpc47m.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, 4)
@@ -18,3 +19,8 @@  int board_early_init_f(void)
 	lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
 	return 0;
 }
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index a051b11..09a52ab 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -37,6 +37,7 @@ 
 
 #define CONFIG_SYS_EARLY_PCI_INIT
 #define CONFIG_PCI_PNP
+#define CONFIG_E1000
 
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
 					"stdout=serial\0" \