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[U-Boot,v3,4/4] arm: interrupt_init: set sp in IRQ/FIQ modes

Message ID 1414362326-6290-5-git-send-email-savoundg@gmail.com
State Superseded
Delegated to: Albert ARIBAUD
Headers show

Commit Message

Georges Savoundararadj Oct. 26, 2014, 10:25 p.m. UTC
Before this commit, the stack addresses for IRQ and FIQ modes,
IRQ_STACK_START and FIQ_STACK_START, were computed in interrupt_init but
they were not used.

This commit sets the stack pointers for IRQ and FIQ modes.

Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

---

Changes in v3:
- None

Changes in v2:
- Reword the commit message

 arch/arm/lib/interrupts.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Albert ARIBAUD Oct. 26, 2014, 11:16 p.m. UTC | #1
Hello Georges,

On Sun, 26 Oct 2014 23:25:26 +0100, Georges Savoundararadj
<savoundg@gmail.com> wrote:
> Before this commit, the stack addresses for IRQ and FIQ modes,
> IRQ_STACK_START and FIQ_STACK_START, were computed in interrupt_init
> but they were not used.
> 
> This commit sets the stack pointers for IRQ and FIQ modes.
> 
> Signed-off-by: Georges Savoundararadj <savoundg@gmail.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> 
> ---
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - Reword the commit message
> 
>  arch/arm/lib/interrupts.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
> index f6b7c03..49c1bf3 100644
> --- a/arch/arm/lib/interrupts.c
> +++ b/arch/arm/lib/interrupts.c
> @@ -34,6 +34,25 @@ int interrupt_init (void)
>  	IRQ_STACK_START_IN = gd->irq_sp + 8;
>  	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
>  
> +	__asm__ __volatile__("msr cpsr_c, %0\n"
> +			     "mov sp, %1\n"
> +			     :
> +			     : "r" (IRQ_MODE | I_BIT | F_BIT),
> +			       "r" (IRQ_STACK_START)
> +			     : "memory");
> +
> +	__asm__ __volatile__("msr cpsr_c, %0\n"
> +			     "mov sp, %1\n"
> +			     :
> +			     : "r" (FIQ_MODE | I_BIT | F_BIT),
> +			       "r" (FIQ_STACK_START)
> +			     : "memory");
> +
> +	__asm__ __volatile__("msr cpsr_c, %0"
> +			     :
> +			     : "r" (SVC_MODE | I_BIT | F_BIT)
> +			     : "memory");

This sequence is trashing bits in CPSR which are unrelated to its
goal, including reserved bits which, as per ARM documentation, are to
be preserved. The sequence should initial CPSR and only change the
mode, I and F bits.

>  	return arch_interrupt_init();
>  }
>  
> -- 
> 2.1.2

Amicalement,
Albert ARIBAUD Oct. 26, 2014, 11:32 p.m. UTC | #2
On Mon, 27 Oct 2014 00:16:46 +0100, Albert ARIBAUD
<albert.u.boot@aribaud.net> wrote:

> be preserved. The sequence should initial CPSR and only change the
> mode, I and F bits.

(grmbl) "... should *read the* initial CPSR and..."

Apologies.


Amicalement,
diff mbox

Patch

diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index f6b7c03..49c1bf3 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -34,6 +34,25 @@  int interrupt_init (void)
 	IRQ_STACK_START_IN = gd->irq_sp + 8;
 	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
 
+	__asm__ __volatile__("msr cpsr_c, %0\n"
+			     "mov sp, %1\n"
+			     :
+			     : "r" (IRQ_MODE | I_BIT | F_BIT),
+			       "r" (IRQ_STACK_START)
+			     : "memory");
+
+	__asm__ __volatile__("msr cpsr_c, %0\n"
+			     "mov sp, %1\n"
+			     :
+			     : "r" (FIQ_MODE | I_BIT | F_BIT),
+			       "r" (FIQ_STACK_START)
+			     : "memory");
+
+	__asm__ __volatile__("msr cpsr_c, %0"
+			     :
+			     : "r" (SVC_MODE | I_BIT | F_BIT)
+			     : "memory");
+
 	return arch_interrupt_init();
 }