From patchwork Sun Oct 26 22:25:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georges Savoundararadj X-Patchwork-Id: 403336 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6B0DE14007D for ; Mon, 27 Oct 2014 09:27:35 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 12E96A73F0; Sun, 26 Oct 2014 23:27:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RcOTArucgga0; Sun, 26 Oct 2014 23:27:33 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 81765A73FC; Sun, 26 Oct 2014 23:27:33 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 95F76A7407 for ; Sun, 26 Oct 2014 23:27:29 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BRiYDRIDR19c for ; Sun, 26 Oct 2014 23:27:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wg0-f52.google.com (mail-wg0-f52.google.com [74.125.82.52]) by theia.denx.de (Postfix) with ESMTPS id 6AC98A73F0 for ; Sun, 26 Oct 2014 23:27:29 +0100 (CET) Received: by mail-wg0-f52.google.com with SMTP id y10so1880471wgg.23 for ; Sun, 26 Oct 2014 15:27:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+G1Nv8BDX+/XQ2wyxiAxY7su5hOMtyYidQRUjIm2Mi4=; b=mddBCYwshafrqPqJxlZ8EYc9EkUL9MdYdGg+iU4zKYMgQqOvMZ11U1WWoPrYNEh6IZ tVBXw8O37xvSORB1ZAzcImEYlCaJ5CU5kM8EdCQnxsGk9eOxuyIuUj0UC9hUU/YrcPO6 VM8DViDKP10/EA0sqDmrc8jIZv9sK3cy9bzNgKT4DdVFRplXdlbmUcNQMOemb4wO/9Kf q64EVwbmv9IhKxXrEItADVR3Ynvd3H2OI3d1kQap3BZzqE+i8qRnhg940uyBLjY6UBHt KeEg2d8b5tHw+4ri76SxBSyhOw5VKZlWNVOG0VOgcOodk6uVegBz62nhmKCqkfYkJapU D9HA== X-Received: by 10.194.62.238 with SMTP id b14mr18051960wjs.46.1414362449158; Sun, 26 Oct 2014 15:27:29 -0700 (PDT) Received: from localhost.localdomain (vit94-5-82-243-49-132.fbx.proxad.net. [82.243.49.132]) by mx.google.com with ESMTPSA id ji10sm9774505wid.7.2014.10.26.15.27.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 26 Oct 2014 15:27:28 -0700 (PDT) From: Georges Savoundararadj To: U-Boot Mailing List Date: Sun, 26 Oct 2014 23:25:26 +0100 Message-Id: <1414362326-6290-5-git-send-email-savoundg@gmail.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1414362326-6290-1-git-send-email-savoundg@gmail.com> References: <1411847291-1790-1-git-send-email-savoundg@gmail.com> <1414362326-6290-1-git-send-email-savoundg@gmail.com> Subject: [U-Boot] [PATCH v3 4/4] arm: interrupt_init: set sp in IRQ/FIQ modes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Before this commit, the stack addresses for IRQ and FIQ modes, IRQ_STACK_START and FIQ_STACK_START, were computed in interrupt_init but they were not used. This commit sets the stack pointers for IRQ and FIQ modes. Signed-off-by: Georges Savoundararadj Cc: Albert Aribaud --- Changes in v3: - None Changes in v2: - Reword the commit message arch/arm/lib/interrupts.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index f6b7c03..49c1bf3 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -34,6 +34,25 @@ int interrupt_init (void) IRQ_STACK_START_IN = gd->irq_sp + 8; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; + __asm__ __volatile__("msr cpsr_c, %0\n" + "mov sp, %1\n" + : + : "r" (IRQ_MODE | I_BIT | F_BIT), + "r" (IRQ_STACK_START) + : "memory"); + + __asm__ __volatile__("msr cpsr_c, %0\n" + "mov sp, %1\n" + : + : "r" (FIQ_MODE | I_BIT | F_BIT), + "r" (FIQ_STACK_START) + : "memory"); + + __asm__ __volatile__("msr cpsr_c, %0" + : + : "r" (SVC_MODE | I_BIT | F_BIT) + : "memory"); + return arch_interrupt_init(); }