| Message ID | a908ab327f59bc6a59881d61bb62e880572113ad.1364962908.git.peter.crosthwaite@xilinx.com |
|---|---|
| State | New |
| Headers | show |
On 3 April 2013 05:33, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote: > The CTRL register was RAZ/WI on some of the RW bits. Even though the > function behind these bits is invalid in QEMU, they should still be > guest accessible. Fix. > > Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> > --- > > hw/xilinx_spips.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c > index 16c2e1d..a2019e4 100644 > --- a/hw/xilinx_spips.c > +++ b/hw/xilinx_spips.c > @@ -341,7 +341,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, > addr >>= 2; > switch (addr) { > case R_CONFIG: > - mask = 0x0002FFFF; > + mask = 0x840AFFFF; > break; > case R_INTR_STATUS: > ret = s->regs[addr] & IXR_ALL; > @@ -404,7 +404,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, > addr >>= 2; > switch (addr) { > case R_CONFIG: > - mask = 0x0002FFFF; > + mask = 0x840AFFFF; > if (value & MAN_START_COM) { > man_start_com = 1; > } > -- > 1.7.0.4 > Maybe the magic number for 'implemented bits in the register' deserves a #define ? -- PMM
Hi Peter, On Sat, Apr 6, 2013 at 4:57 AM, Peter Maydell <peter.maydell@linaro.org> wrote: > On 3 April 2013 05:33, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote: >> The CTRL register was RAZ/WI on some of the RW bits. Even though the >> function behind these bits is invalid in QEMU, they should still be >> guest accessible. Fix. >> >> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> >> --- >> >> hw/xilinx_spips.c | 4 ++-- >> 1 files changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c >> index 16c2e1d..a2019e4 100644 >> --- a/hw/xilinx_spips.c >> +++ b/hw/xilinx_spips.c >> @@ -341,7 +341,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, >> addr >>= 2; >> switch (addr) { >> case R_CONFIG: >> - mask = 0x0002FFFF; >> + mask = 0x840AFFFF; >> break; >> case R_INTR_STATUS: >> ret = s->regs[addr] & IXR_ALL; >> @@ -404,7 +404,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, >> addr >>= 2; >> switch (addr) { >> case R_CONFIG: >> - mask = 0x0002FFFF; >> + mask = 0x840AFFFF; >> if (value & MAN_START_COM) { >> man_start_com = 1; >> } >> -- >> 1.7.0.4 >> > > > Maybe the magic number for 'implemented bits in the register' > deserves a #define ? > Took the reverse approach, and defined the unimplemented (reserved) bits and inverted to make mask. Regards, Peter > -- PMM >
diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c index 16c2e1d..a2019e4 100644 --- a/hw/xilinx_spips.c +++ b/hw/xilinx_spips.c @@ -341,7 +341,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = 0x840AFFFF; break; case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; @@ -404,7 +404,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = 0x840AFFFF; if (value & MAN_START_COM) { man_start_com = 1; }
The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> --- hw/xilinx_spips.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)