From patchwork Wed Apr 3 04:33:02 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 233228 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BC5722C014F for ; Wed, 3 Apr 2013 15:37:43 +1100 (EST) Received: from localhost ([::1]:50262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNFS8-00038f-GE for incoming@patchwork.ozlabs.org; Wed, 03 Apr 2013 00:37:40 -0400 Received: from eggs.gnu.org ([208.118.235.92]:60247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNFRa-0002k7-E9 for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:37:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UNFRZ-00074R-LL for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:37:06 -0400 Received: from mail-pb0-f42.google.com ([209.85.160.42]:35229) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UNFRZ-00074L-Fo for qemu-devel@nongnu.org; Wed, 03 Apr 2013 00:37:05 -0400 Received: by mail-pb0-f42.google.com with SMTP id up7so624176pbc.29 for ; Tue, 02 Apr 2013 21:37:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:in-reply-to:references:x-gm-message-state; bh=SZSdKIN9K6e0saReohXiBcopJhUrf5WyFkwTofF6e7w=; b=e6uAzALZ4RiztDuWO7CeW/r8gV2b5CvEQFVftOTzHTBUnT4tnkYNpe1sBYaK5As6rl 0qYm0cpkAKIvyDJKuNeJruOL278mh3wOg43kR97FoRHRMj3ZmyYNsMjXb6Xx3Y9CSTmw 4tezkPmobvd93O08NbIojzyxF/1nAUmB2UNabIcZEpePjbC+/weybbKQPg6gZpyqIuEd YM88LNWiRX7LIzvukb3Ta/bh0QeI2jtl2glLTTMt0SXATP+2/Md1cqQMjpZ3N42jbjd+ uG5jiQm/EDDk0sWvIGaYhjpw3GM6+7H0XCrXX6kDN5iTT1njtYYfg5pOZxUczXlMTGJv yHvA== X-Received: by 10.68.41.197 with SMTP id h5mr251615pbl.88.1364963824804; Tue, 02 Apr 2013 21:37:04 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id ef3sm5128625pad.20.2013.04.02.21.37.02 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Tue, 02 Apr 2013 21:37:03 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Wed, 3 Apr 2013 14:33:02 +1000 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <475b23a3c56ec5ee1a8652f33e0a12d0bb4ac7f6.1364962908.git.peter.crosthwaite@xilinx.com> References: <475b23a3c56ec5ee1a8652f33e0a12d0bb4ac7f6.1364962908.git.peter.crosthwaite@xilinx.com> In-Reply-To: References: X-Gm-Message-State: ALoCoQkadLqwiUqpH94GKAvHgbViEZ5Wd06hD/vAKd3M2QNUGV+F0HL7BQRJkq52QU+WzS6a53e4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.160.42 Cc: Peter Crosthwaite Subject: [Qemu-devel] [PATCH arm-devs v1 10/15] xilinx_spips: Fix CTRL register RW bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The CTRL register was RAZ/WI on some of the RW bits. Even though the function behind these bits is invalid in QEMU, they should still be guest accessible. Fix. Signed-off-by: Peter Crosthwaite --- hw/xilinx_spips.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/xilinx_spips.c b/hw/xilinx_spips.c index 16c2e1d..a2019e4 100644 --- a/hw/xilinx_spips.c +++ b/hw/xilinx_spips.c @@ -341,7 +341,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = 0x840AFFFF; break; case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; @@ -404,7 +404,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, addr >>= 2; switch (addr) { case R_CONFIG: - mask = 0x0002FFFF; + mask = 0x840AFFFF; if (value & MAN_START_COM) { man_start_com = 1; }