@@ -24,6 +24,13 @@
#define __CONFIG_H
/*
+ * Define this when NOR U-Boot is loaded directly from flash as it
+ * must perform all the low level initialization itself.
+ *
+#define CONFIG_DIRECT_NOR_BOOT
+*/
+
+/*
* Board
*/
#define CONFIG_DRIVER_TI_EMAC
@@ -43,10 +50,19 @@
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_TEXT_BASE 0xc1080000
#define CONFIG_SYS_DA850_PLL_INIT
#define CONFIG_SYS_DA850_DDR_INIT
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
+#define CONFIG_DA850_LOWLEVEL
+#else
+#define CONFIG_SYS_TEXT_BASE 0xc1080000
+#endif
+
/*
* Memory Info
*/
@@ -373,6 +389,7 @@
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000
#endif
+#ifndef CONFIG_USE_NOR
/* defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_SERIAL_SUPPORT
@@ -382,9 +399,16 @@
#define CONFIG_SPL_STACK 0x8001ff00
#define CONFIG_SPL_TEXT_BASE 0x80000000
#define CONFIG_SPL_MAX_SIZE 32768
+#endif
+
/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
+
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
+#else
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_DIRECT_NOR_BOOT */
#endif /* __CONFIG_H */