| Message ID | 20191205230428.23497-2-sjg@chromium.org |
|---|---|
| State | Superseded |
| Delegated to: | Bin Meng |
| Headers | show |
| Series | [1/4] serial: n16550: Support run-time configuration | expand |
On Fri, Dec 6, 2019 at 7:04 AM Simon Glass <sjg@chromium.org> wrote: > > Since mid 2016, coreboot has additional fields in the serial struct that > it passes down to U-Boot. Add these so we are in sync. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > arch/x86/include/asm/coreboot_tables.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h index 2c54e24e02..61de0077d7 100644 --- a/arch/x86/include/asm/coreboot_tables.h +++ b/arch/x86/include/asm/coreboot_tables.h @@ -97,6 +97,25 @@ struct cb_serial { u32 type; u32 baseaddr; u32 baud; + u32 regwidth; + + /* + * Crystal or input frequency to the chip containing the UART. + * Provide the board specific details to allow the payload to + * initialize the chip containing the UART and make independent + * decisions as to which dividers to select and their values + * to eventually arrive at the desired console baud-rate. + */ + u32 input_hertz; + + /* + * UART PCI address: bus, device, function + * 1 << 31 - Valid bit, PCI UART in use + * Bus << 20 + * Device << 15 + * Function << 12 + */ + u32 uart_pci_addr; }; #define CB_TAG_CONSOLE 0x0010
Since mid 2016, coreboot has additional fields in the serial struct that it passes down to U-Boot. Add these so we are in sync. Signed-off-by: Simon Glass <sjg@chromium.org> --- arch/x86/include/asm/coreboot_tables.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)