diff mbox

[U-Boot] powerpc/mpc8xxx: fix DDR data width checking

Message ID 1309206925-27881-1-git-send-email-yorksun@freescale.com
State Accepted
Commit 4c99cb9190358e11ad96ba95b38d1e83cc053b46
Headers show

Commit Message

York Sun June 27, 2011, 8:35 p.m. UTC 
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data
width and primary sdram width. The latter one has different meaning for DDR3.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/options.c |   35 ++++++++++++++++++++++++-------
 1 files changed, 27 insertions(+), 8 deletions(-)

Comments

Kumar Gala July 11, 2011, 5:55 p.m. UTC | #1 
On Jun 27, 2011, at 3:35 PM, York Sun wrote:

> Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data
> width and primary sdram width. The latter one has different meaning for DDR3.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> arch/powerpc/cpu/mpc8xxx/ddr/options.c |   35 ++++++++++++++++++++++++-------
> 1 files changed, 27 insertions(+), 8 deletions(-)

applied

- k
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 02efe58..bd9c466 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -423,14 +423,33 @@  unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 * presuming all dimms are similar
 	 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
 	 */
-	if (pdimm[0].primary_sdram_width == 64)
-		popts->data_bus_width = 0;
-	else if (pdimm[0].primary_sdram_width == 32)
-		popts->data_bus_width = 1;
-	else if (pdimm[0].primary_sdram_width == 16)
-		popts->data_bus_width = 2;
-	else
-		panic("Error: invalid primary sdram width!\n");
+#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2)
+	if (pdimm[0].n_ranks != 0) {
+		if ((pdimm[0].data_width >= 64) && \
+			(pdimm[0].data_width <= 72))
+			popts->data_bus_width = 0;
+		else if ((pdimm[0].data_width >= 32) || \
+			(pdimm[0].data_width <= 40))
+			popts->data_bus_width = 1;
+		else {
+			panic("Error: data width %u is invalid!\n",
+				pdimm[0].data_width);
+		}
+	}
+#else
+	if (pdimm[0].n_ranks != 0) {
+		if (pdimm[0].primary_sdram_width == 64)
+			popts->data_bus_width = 0;
+		else if (pdimm[0].primary_sdram_width == 32)
+			popts->data_bus_width = 1;
+		else if (pdimm[0].primary_sdram_width == 16)
+			popts->data_bus_width = 2;
+		else {
+			panic("Error: primary sdram width %u is invalid!\n",
+				pdimm[0].primary_sdram_width);
+		}
+	}
+#endif
 
 	/* Choose burst length. */
 #if defined(CONFIG_FSL_DDR3)