From patchwork Mon Jun 27 20:35:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 102273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4452EB6F65 for ; Tue, 28 Jun 2011 06:35:51 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 413B6280C4; Mon, 27 Jun 2011 22:35:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rThQdXgXHlNW; Mon, 27 Jun 2011 22:35:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 12E99280C9; Mon, 27 Jun 2011 22:35:48 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 781EA280C9 for ; Mon, 27 Jun 2011 22:35:45 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zC8qZ4Dmkhbh for ; Mon, 27 Jun 2011 22:35:44 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from VA3EHSOBE005.bigfish.com (va3ehsobe005.messaging.microsoft.com [216.32.180.31]) by theia.denx.de (Postfix) with ESMTPS id 42D5A280C4 for ; Mon, 27 Jun 2011 22:35:42 +0200 (CEST) Received: from mail194-va3-R.bigfish.com (10.7.14.253) by VA3EHSOBE005.bigfish.com (10.7.40.25) with Microsoft SMTP Server id 14.1.225.22; Mon, 27 Jun 2011 20:35:41 +0000 Received: from mail194-va3 (localhost.localdomain [127.0.0.1]) by mail194-va3-R.bigfish.com (Postfix) with ESMTP id 110DE17B0226 for ; Mon, 27 Jun 2011 20:35:41 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail194-va3 (localhost.localdomain [127.0.0.1]) by mail194-va3 (MessageSwitch) id 1309206940919201_23426; Mon, 27 Jun 2011 20:35:40 +0000 (UTC) Received: from VA3EHSMHS025.bigfish.com (unknown [10.7.14.241]) by mail194-va3.bigfish.com (Postfix) with ESMTP id DAEC8153804B for ; Mon, 27 Jun 2011 20:35:40 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS025.bigfish.com (10.7.99.35) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 27 Jun 2011 20:35:28 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.289.8; Mon, 27 Jun 2011 15:35:27 -0500 Received: from localhost.localdomain (mvp-10-214-72-23.am.freescale.net [10.214.72.23]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p5RKZQNn008953; Mon, 27 Jun 2011 15:35:27 -0500 (CDT) From: York Sun To: Date: Mon, 27 Jun 2011 13:35:25 -0700 Message-ID: <1309206925-27881-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH] powerpc/mpc8xxx: fix DDR data width checking X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data width and primary sdram width. The latter one has different meaning for DDR3. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 35 ++++++++++++++++++++++++------- 1 files changed, 27 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 02efe58..bd9c466 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -423,14 +423,33 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * presuming all dimms are similar * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ - if (pdimm[0].primary_sdram_width == 64) - popts->data_bus_width = 0; - else if (pdimm[0].primary_sdram_width == 32) - popts->data_bus_width = 1; - else if (pdimm[0].primary_sdram_width == 16) - popts->data_bus_width = 2; - else - panic("Error: invalid primary sdram width!\n"); +#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2) + if (pdimm[0].n_ranks != 0) { + if ((pdimm[0].data_width >= 64) && \ + (pdimm[0].data_width <= 72)) + popts->data_bus_width = 0; + else if ((pdimm[0].data_width >= 32) || \ + (pdimm[0].data_width <= 40)) + popts->data_bus_width = 1; + else { + panic("Error: data width %u is invalid!\n", + pdimm[0].data_width); + } + } +#else + if (pdimm[0].n_ranks != 0) { + if (pdimm[0].primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm[0].primary_sdram_width == 32) + popts->data_bus_width = 1; + else if (pdimm[0].primary_sdram_width == 16) + popts->data_bus_width = 2; + else { + panic("Error: primary sdram width %u is invalid!\n", + pdimm[0].primary_sdram_width); + } + } +#endif /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3)