| Message ID | 20131111192602.GA22118@amd.pavel.ucw.cz |
|---|---|
| State | Not Applicable |
| Delegated to: | Albert ARIBAUD |
| Headers | show |
Hi Pavel, On Mon, 2013-11-11 at 20:26 +0100, ZY - pavel wrote: > Altera Cyclone 5 board is very different board (big, rectangular, > expensive) than EBV Socrates (small, circular, cheap) board. Different > parts are used there, too, but same configuration of u-boot works on > both. Nevertheless, printing wrong name confuses users. > > Therefore this splits the configuration so that u-boot knows they are > different. So far it is only used for correcting the puts, but there > may be other uses in future. > > Signed-off-by: Pavel Machek <pavel@denx.de> > Looks good to me. Reviewed-by: Chin Liang See <clsee@altera.com> In fact, we already make this change at our git at http://rocketboards.org/gitweb/?p=u-boot-socfpga.git;a=shortlog;h=refs/heads/socfpga_v2013.01.01. Hopefully I can continue to upstream few new patches in coming days. Thanks Chin Liang
On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > Altera Cyclone 5 board is very different board (big, rectangular, > expensive) than EBV Socrates (small, circular, cheap) board. Different > parts are used there, too, but same configuration of u-boot works on > both. Nevertheless, printing wrong name confuses users. > > Therefore this splits the configuration so that u-boot knows they are > different. So far it is only used for correcting the puts, but there > may be other uses in future. > > Signed-off-by: Pavel Machek <pavel@denx.de> Is there any way at run time to tell which board we are on?
On 11/11/2013 09:33 PM, Tom Rini wrote: > On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > >> Altera Cyclone 5 board is very different board (big, rectangular, >> expensive) than EBV Socrates (small, circular, cheap) board. Different >> parts are used there, too, but same configuration of u-boot works on >> both. Nevertheless, printing wrong name confuses users. >> >> Therefore this splits the configuration so that u-boot knows they are >> different. So far it is only used for correcting the puts, but there >> may be other uses in future. >> >> Signed-off-by: Pavel Machek <pavel@denx.de> > > Is there any way at run time to tell which board we are on? Why do you care about board name in general? Just write that it is socfpga and that's it. Thanks, Michal
Hi Tom, > On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > >> Altera Cyclone 5 board is very different board (big, rectangular, >> expensive) than EBV Socrates (small, circular, cheap) board. Different >> parts are used there, too, but same configuration of u-boot works on >> both. Nevertheless, printing wrong name confuses users. >> >> Therefore this splits the configuration so that u-boot knows they are >> different. So far it is only used for correcting the puts, but there >> may be other uses in future. >> >> Signed-off-by: Pavel Machek <pavel@denx.de> > > Is there any way at run time to tell which board we are on? I'll try to find out, but currently I don't know of any way. Best wishes Detlev
Hi Michal, > On 11/11/2013 09:33 PM, Tom Rini wrote: >> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: >> >>> Altera Cyclone 5 board is very different board (big, rectangular, >>> expensive) than EBV Socrates (small, circular, cheap) board. Different >>> parts are used there, too, but same configuration of u-boot works on >>> both. Nevertheless, printing wrong name confuses users. >>> >>> Therefore this splits the configuration so that u-boot knows they are >>> different. So far it is only used for correcting the puts, but there >>> may be other uses in future. >>> >>> Signed-off-by: Pavel Machek <pavel@denx.de> >> >> Is there any way at run time to tell which board we are on? > > Why do you care about board name in general? We care for board names for a very long time in U-Boot and I'd like to keep this. I actually expect a sensible board name on any platform that I touch. The board name is an important extra information additional to the SoC name. So the question is the other way round - since when do we _not_ care about board names? Cheers Detlev
On 11/12/2013 10:56 AM, Detlev Zundel wrote: > Hi Michal, > >> On 11/11/2013 09:33 PM, Tom Rini wrote: >>> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: >>> >>>> Altera Cyclone 5 board is very different board (big, rectangular, >>>> expensive) than EBV Socrates (small, circular, cheap) board. Different >>>> parts are used there, too, but same configuration of u-boot works on >>>> both. Nevertheless, printing wrong name confuses users. >>>> >>>> Therefore this splits the configuration so that u-boot knows they are >>>> different. So far it is only used for correcting the puts, but there >>>> may be other uses in future. >>>> >>>> Signed-off-by: Pavel Machek <pavel@denx.de> >>> >>> Is there any way at run time to tell which board we are on? >> >> Why do you care about board name in general? > > We care for board names for a very long time in U-Boot and I'd like to > keep this. I actually expect a sensible board name on any platform that > I touch. The board name is an important extra information additional to > the SoC name. So the question is the other way round - since when do we > _not_ care about board names? There could be i2c memory on board where you can find out this information but that's problematic if it is empty or you want to use this i2c for something else. For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design (if user is smart enough board name is the part of hw design name). For zynq/socfpga sensible solution is probably to load this name for DTS. Thanks, Michal
Hi all, On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: > On 11/12/2013 10:56 AM, Detlev Zundel wrote: > > Hi Michal, > > > >> On 11/11/2013 09:33 PM, Tom Rini wrote: > >>> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > >>> > >>>> Altera Cyclone 5 board is very different board (big, rectangular, > >>>> expensive) than EBV Socrates (small, circular, cheap) board. Different > >>>> parts are used there, too, but same configuration of u-boot works on > >>>> both. Nevertheless, printing wrong name confuses users. > >>>> > >>>> Therefore this splits the configuration so that u-boot knows they are > >>>> different. So far it is only used for correcting the puts, but there > >>>> may be other uses in future. > >>>> > >>>> Signed-off-by: Pavel Machek <pavel@denx.de> > >>> > >>> Is there any way at run time to tell which board we are on? > >> > >> Why do you care about board name in general? > > > > We care for board names for a very long time in U-Boot and I'd like to > > keep this. I actually expect a sensible board name on any platform that > > I touch. The board name is an important extra information additional to > > the SoC name. So the question is the other way round - since when do we > > _not_ care about board names? > > There could be i2c memory on board where you can find out this information but that's > problematic if it is empty or you want to use this i2c for something else. > For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design > (if user is smart enough board name is the part of hw design name). > For zynq/socfpga sensible solution is probably to load this name for DTS. > Currently, the SOCFPGA SPL is customized through a set of handoff files which located at board folders. These handoff files are generated by tools based on board and user design in FPGA. With that, not much decision being made during run time based on the board. With this handoff and tools approach, it will shield off the complexity of hardware configuration and errors (if user change it manually without tools help). Thanks Chin Liang > Thanks, > Michal >
On 11/12/2013 03:46 PM, Chin Liang See wrote: > Hi all, > > On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: >> On 11/12/2013 10:56 AM, Detlev Zundel wrote: >>> Hi Michal, >>> >>>> On 11/11/2013 09:33 PM, Tom Rini wrote: >>>>> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: >>>>> >>>>>> Altera Cyclone 5 board is very different board (big, rectangular, >>>>>> expensive) than EBV Socrates (small, circular, cheap) board. Different >>>>>> parts are used there, too, but same configuration of u-boot works on >>>>>> both. Nevertheless, printing wrong name confuses users. >>>>>> >>>>>> Therefore this splits the configuration so that u-boot knows they are >>>>>> different. So far it is only used for correcting the puts, but there >>>>>> may be other uses in future. >>>>>> >>>>>> Signed-off-by: Pavel Machek <pavel@denx.de> >>>>> >>>>> Is there any way at run time to tell which board we are on? >>>> >>>> Why do you care about board name in general? >>> >>> We care for board names for a very long time in U-Boot and I'd like to >>> keep this. I actually expect a sensible board name on any platform that >>> I touch. The board name is an important extra information additional to >>> the SoC name. So the question is the other way round - since when do we >>> _not_ care about board names? >> >> There could be i2c memory on board where you can find out this information but that's >> problematic if it is empty or you want to use this i2c for something else. >> For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design >> (if user is smart enough board name is the part of hw design name). >> For zynq/socfpga sensible solution is probably to load this name for DTS. >> > > Currently, the SOCFPGA SPL is customized through a set of handoff files > which located at board folders. These handoff files are generated by > tools based on board and user design in FPGA. With that, not much > decision being made during run time based on the board. With this > handoff and tools approach, it will shield off the complexity of > hardware configuration and errors (if user change it manually without > tools help). Thanks Which nice copy of our approach. :-) But anyway I believe that you are also generating one macro which define name of this configuration based on hw design/board you are using. And then you can use this macro for showing board/design name in u-boot. Thanks, Michal
On Tue, Nov 12, 2013 at 10:56:29AM +0100, Detlev Zundel wrote: > Hi Michal, > > > On 11/11/2013 09:33 PM, Tom Rini wrote: > >> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > >> > >>> Altera Cyclone 5 board is very different board (big, rectangular, > >>> expensive) than EBV Socrates (small, circular, cheap) board. Different > >>> parts are used there, too, but same configuration of u-boot works on > >>> both. Nevertheless, printing wrong name confuses users. > >>> > >>> Therefore this splits the configuration so that u-boot knows they are > >>> different. So far it is only used for correcting the puts, but there > >>> may be other uses in future. > >>> > >>> Signed-off-by: Pavel Machek <pavel@denx.de> > >> > >> Is there any way at run time to tell which board we are on? > > > > Why do you care about board name in general? > > We care for board names for a very long time in U-Boot and I'd like to > keep this. I actually expect a sensible board name on any platform that > I touch. The board name is an important extra information additional to > the SoC name. So the question is the other way round - since when do we > _not_ care about board names? We have a few different and somewhat conflicting concerns right now, and this particular platform is an example of a few of them: 1) It's not only possible, but desirable (seemingly, in this case) to support N boards with a single binary. The space-cost is outweighed by the usability-gain. We're seeing this in Freescale and TI parts, and I bet if I looked a tiny bit harder, other vendors too. 2) We want to know what particular board we're on, and perhaps even as part of deployment build something more trimmed down to just what we're running on.
On Tue, Nov 12, 2013 at 9:17 AM, Michal Simek <monstr@monstr.eu> wrote: > On 11/12/2013 03:46 PM, Chin Liang See wrote: > > Hi all, > > > > On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: > >> On 11/12/2013 10:56 AM, Detlev Zundel wrote: > >>> Hi Michal, > >>> > >>>> On 11/11/2013 09:33 PM, Tom Rini wrote: > >>>>> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > >>>>> > >>>>>> Altera Cyclone 5 board is very different board (big, rectangular, > >>>>>> expensive) than EBV Socrates (small, circular, cheap) board. > Different > >>>>>> parts are used there, too, but same configuration of u-boot works on > >>>>>> both. Nevertheless, printing wrong name confuses users. > >>>>>> > >>>>>> Therefore this splits the configuration so that u-boot knows they > are > >>>>>> different. So far it is only used for correcting the puts, but there > >>>>>> may be other uses in future. > >>>>>> > >>>>>> Signed-off-by: Pavel Machek <pavel@denx.de> > >>>>> > >>>>> Is there any way at run time to tell which board we are on? > >>>> > >>>> Why do you care about board name in general? > >>> > >>> We care for board names for a very long time in U-Boot and I'd like to > >>> keep this. I actually expect a sensible board name on any platform > that > >>> I touch. The board name is an important extra information additional > to > >>> the SoC name. So the question is the other way round - since when do > we > >>> _not_ care about board names? > >> > >> There could be i2c memory on board where you can find out this > information but that's > >> problematic if it is empty or you want to use this i2c for something > else. > >> For all microblaze boards I use XILINX_BOARD_NAME which reflects hw > design > >> (if user is smart enough board name is the part of hw design name). > >> For zynq/socfpga sensible solution is probably to load this name for > DTS. > >> > > > > Currently, the SOCFPGA SPL is customized through a set of handoff files > > which located at board folders. These handoff files are generated by > > tools based on board and user design in FPGA. With that, not much > > decision being made during run time based on the board. With this > > handoff and tools approach, it will shield off the complexity of > > hardware configuration and errors (if user change it manually without > > tools help). Thanks > > Which nice copy of our approach. :-) > Ugh...that came from you guys? I can't stand that approach. Coming from the i.MX world, this makes the end user so reliant on proprietary tools. Dinh > But anyway I believe that you are also generating one macro which define > name of this configuration based on hw design/board you are using. > And then you can use this macro for showing board/design name in u-boot. > > Thanks, > Michal > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ > Maintainer of Linux kernel - Xilinx Zynq ARM architecture > Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform > > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > >
On Tue, 2013-11-12 at 16:17 +0100, Michal Simek wrote: > On 11/12/2013 03:46 PM, Chin Liang See wrote: > > Hi all, > > > > On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: > >> On 11/12/2013 10:56 AM, Detlev Zundel wrote: > >>> Hi Michal, > >>> > >>>> On 11/11/2013 09:33 PM, Tom Rini wrote: > >>>>> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: > >>>>> > >>>>>> Altera Cyclone 5 board is very different board (big, rectangular, > >>>>>> expensive) than EBV Socrates (small, circular, cheap) board. Different > >>>>>> parts are used there, too, but same configuration of u-boot works on > >>>>>> both. Nevertheless, printing wrong name confuses users. > >>>>>> > >>>>>> Therefore this splits the configuration so that u-boot knows they are > >>>>>> different. So far it is only used for correcting the puts, but there > >>>>>> may be other uses in future. > >>>>>> > >>>>>> Signed-off-by: Pavel Machek <pavel@denx.de> > >>>>> > >>>>> Is there any way at run time to tell which board we are on? > >>>> > >>>> Why do you care about board name in general? > >>> > >>> We care for board names for a very long time in U-Boot and I'd like to > >>> keep this. I actually expect a sensible board name on any platform that > >>> I touch. The board name is an important extra information additional to > >>> the SoC name. So the question is the other way round - since when do we > >>> _not_ care about board names? > >> > >> There could be i2c memory on board where you can find out this information but that's > >> problematic if it is empty or you want to use this i2c for something else. > >> For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design > >> (if user is smart enough board name is the part of hw design name). > >> For zynq/socfpga sensible solution is probably to load this name for DTS. > >> > > > > Currently, the SOCFPGA SPL is customized through a set of handoff files > > which located at board folders. These handoff files are generated by > > tools based on board and user design in FPGA. With that, not much > > decision being made during run time based on the board. With this > > handoff and tools approach, it will shield off the complexity of > > hardware configuration and errors (if user change it manually without > > tools help). Thanks > > Which nice copy of our approach. :-) Hmmm... is it true? This approach being used since few years back at NIOS soft processor. Besides that, we are utilizing the SPL framework for our second stage boot loader. I believe you guys are not using SPL right? It seems you guys would need tools to generate and even build you guys own version of boot loader. It creates high dependency for user to your tools. For our solution, customer can just grab the code from git and build it using the normal U-Boot way (if they don't want to use the tools). With the SPL also, we are taking advantage of open source community power to make our second stage boot loader more powerful and user friendly to user. Our user can grab any drivers or leverage the supports from the open community too. I believe that is the power of open source :) Chin Liang > But anyway I believe that you are also generating one macro which define > name of this configuration based on hw design/board you are using. > And then you can use this macro for showing board/design name in u-boot. > > Thanks, > Michal >
On 11/13/2013 03:39 PM, Chin Liang See wrote: > On Tue, 2013-11-12 at 16:17 +0100, Michal Simek wrote: >> On 11/12/2013 03:46 PM, Chin Liang See wrote: >>> Hi all, >>> >>> On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote: >>>> On 11/12/2013 10:56 AM, Detlev Zundel wrote: >>>>> Hi Michal, >>>>> >>>>>> On 11/11/2013 09:33 PM, Tom Rini wrote: >>>>>>> On Mon, Nov 11, 2013 at 08:26:02PM +0100, Pavel Machek wrote: >>>>>>> >>>>>>>> Altera Cyclone 5 board is very different board (big, rectangular, >>>>>>>> expensive) than EBV Socrates (small, circular, cheap) board. Different >>>>>>>> parts are used there, too, but same configuration of u-boot works on >>>>>>>> both. Nevertheless, printing wrong name confuses users. >>>>>>>> >>>>>>>> Therefore this splits the configuration so that u-boot knows they are >>>>>>>> different. So far it is only used for correcting the puts, but there >>>>>>>> may be other uses in future. >>>>>>>> >>>>>>>> Signed-off-by: Pavel Machek <pavel@denx.de> >>>>>>> >>>>>>> Is there any way at run time to tell which board we are on? >>>>>> >>>>>> Why do you care about board name in general? >>>>> >>>>> We care for board names for a very long time in U-Boot and I'd like to >>>>> keep this. I actually expect a sensible board name on any platform that >>>>> I touch. The board name is an important extra information additional to >>>>> the SoC name. So the question is the other way round - since when do we >>>>> _not_ care about board names? >>>> >>>> There could be i2c memory on board where you can find out this information but that's >>>> problematic if it is empty or you want to use this i2c for something else. >>>> For all microblaze boards I use XILINX_BOARD_NAME which reflects hw design >>>> (if user is smart enough board name is the part of hw design name). >>>> For zynq/socfpga sensible solution is probably to load this name for DTS. >>>> >>> >>> Currently, the SOCFPGA SPL is customized through a set of handoff files >>> which located at board folders. These handoff files are generated by >>> tools based on board and user design in FPGA. With that, not much >>> decision being made during run time based on the board. With this >>> handoff and tools approach, it will shield off the complexity of >>> hardware configuration and errors (if user change it manually without >>> tools help). Thanks >> >> Which nice copy of our approach. :-) > > Hmmm... is it true? This approach being used since few years back at > NIOS soft processor. Besides that, we are utilizing the SPL framework > for our second stage boot loader. I believe you guys are not using SPL > right? It seems you guys would need tools to generate and even build you > guys own version of boot loader. It creates high dependency for user to > your tools. Interesting discussion. :-) I believe we will use SPL at some point in future for Microblaze just because of easier maintenance . But will see. I don't understand your point regarding to tool dependency. For DTSes I believe you are also generating this structure from design tools or you can write it by hand. We are also generating U-boot configuration but if someone wants to write it by hand they can. > For our solution, customer can just grab the code from git and build it > using the normal U-Boot way (if they don't want to use the tools). With > the SPL also, we are taking advantage of open source community power to > make our second stage boot loader more powerful and user friendly to > user. Our user can grab any drivers or leverage the supports from the > open community too. I believe that is the power of open source :) We have the same for Microblaze and Zynq. Cheers, Michal
Hi, > >>>> > >>> > >>> Currently, the SOCFPGA SPL is customized through a set of handoff files > >>> which located at board folders. These handoff files are generated by > >>> tools based on board and user design in FPGA. With that, not much > >>> decision being made during run time based on the board. With this > >>> handoff and tools approach, it will shield off the complexity of > >>> hardware configuration and errors (if user change it manually without > >>> tools help). Thanks > >> > >> Which nice copy of our approach. :-) > > > > Hmmm... is it true? This approach being used since few years back at > > NIOS soft processor. Besides that, we are utilizing the SPL framework > > for our second stage boot loader. I believe you guys are not using SPL > > right? It seems you guys would need tools to generate and even build you > > guys own version of boot loader. It creates high dependency for user to > > your tools. > > Interesting discussion. :-) > I believe we will use SPL at some point in future for Microblaze > just because of easier maintenance . But will see. Yup, utilizing SPL will gain you the power of open source :) > > I don't understand your point regarding to tool dependency. For DTSes > I believe you are also generating this structure from design tools > or you can write it by hand. > We are also generating U-boot configuration but if someone wants to write > it by hand they can. I believe we have misalignment on the term used. For us, second stage bootloader is referring to the bootloader loaded by BootROM. I believe you guys are referring that as FSBL. > > For our solution, customer can just grab the code from git and build it > > using the normal U-Boot way (if they don't want to use the tools). With > > the SPL also, we are taking advantage of open source community power to > > make our second stage boot loader more powerful and user friendly to > > user. Our user can grab any drivers or leverage the supports from the > > open community too. I believe that is the power of open source :) > > We have the same for Microblaze and Zynq. Same as above, I believe both of us are using U-Boot. But for bootloader before U-Boot, we are using SPL while you guys using FSBL which is not SPL framework, right? With that, I believe you guys would need a proprietary tools to compile and build the FSBL. We would not have this dependency when building the SPL code. Thanks Chin Liang > > Cheers, > Michal >
On 11/13/2013 06:57 PM, Chin Liang See wrote: > Hi, > >>>>>> >>>>> >>>>> Currently, the SOCFPGA SPL is customized through a set of handoff files >>>>> which located at board folders. These handoff files are generated by >>>>> tools based on board and user design in FPGA. With that, not much >>>>> decision being made during run time based on the board. With this >>>>> handoff and tools approach, it will shield off the complexity of >>>>> hardware configuration and errors (if user change it manually without >>>>> tools help). Thanks >>>> >>>> Which nice copy of our approach. :-) >>> >>> Hmmm... is it true? This approach being used since few years back at >>> NIOS soft processor. Besides that, we are utilizing the SPL framework >>> for our second stage boot loader. I believe you guys are not using SPL >>> right? It seems you guys would need tools to generate and even build you >>> guys own version of boot loader. It creates high dependency for user to >>> your tools. >> >> Interesting discussion. :-) >> I believe we will use SPL at some point in future for Microblaze >> just because of easier maintenance . But will see. > > Yup, utilizing SPL will gain you the power of open source :) I agree with you but still we both have strong dependency on tools regarding to configuration that's why you can do it without tools but still you have to go through tools to get at least bitstream for PL. >> >> I don't understand your point regarding to tool dependency. For DTSes >> I believe you are also generating this structure from design tools >> or you can write it by hand. >> We are also generating U-boot configuration but if someone wants to write >> it by hand they can. > > I believe we have misalignment on the term used. For us, second stage > bootloader is referring to the bootloader loaded by BootROM. I believe > you guys are referring that as FSBL. zynq: bootrom->fsbl->u-boot-> whatever or bootrom->fsbl-> whatever microblaze: fsboot->u-boot->whatever. For you I believe it is for socfpga bootrom->SPL->u-boot-> whatever or bootrom->SPL->whatever I am not quite sure what you are using for NIOS. >>> For our solution, customer can just grab the code from git and build it >>> using the normal U-Boot way (if they don't want to use the tools). With >>> the SPL also, we are taking advantage of open source community power to >>> make our second stage boot loader more powerful and user friendly to >>> user. Our user can grab any drivers or leverage the supports from the >>> open community too. I believe that is the power of open source :) >> >> We have the same for Microblaze and Zynq. > > Same as above, I believe both of us are using U-Boot. But for bootloader > before U-Boot, we are using SPL while you guys using FSBL which is not > SPL framework, right? With that, I believe you guys would need a > proprietary tools to compile and build the FSBL. We would not have this > dependency when building the SPL code. Yes that's correct. Thanks, Michal
Hi Pavel, On Mon, 11 Nov 2013 20:26:02 +0100, Pavel Machek <pavel@denx.de> wrote: > > Altera Cyclone 5 board is very different board (big, rectangular, > expensive) than EBV Socrates (small, circular, cheap) board. Different > parts are used there, too, but same configuration of u-boot works on > both. Nevertheless, printing wrong name confuses users. > > Therefore this splits the configuration so that u-boot knows they are > different. So far it is only used for correcting the puts, but there > may be other uses in future. > > Signed-off-by: Pavel Machek <pavel@denx.de> [weird: I don't see the commit separation line here ("---"). Not that it matters much, just surprising.] I assume the discussion on this patch is not actually related to the change itself, which is thus OK. However, it does not apply cleanly on current ARM tree. Amicalement,
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 576066b..4540b1b 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -26,7 +26,7 @@ int print_cpuinfo(void) */ int checkboard(void) { - puts("BOARD : Altera SOCFPGA Cyclone5 Board\n"); + puts("BOARD : " ALTERA_BOARD_NAME "\n"); return 0; } diff --git a/boards.cfg b/boards.cfg index 375f2d4..20534c3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -340,6 +340,7 @@ Active arm armv7 rmobile kmc kzm9g Active arm armv7 s5pc1xx samsung goni s5p_goni - Minkyu Kang <mk7.kang@samsung.com> Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com> Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 socfpga altera socfpga socfpga_socrates - - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org> Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h new file mode 100644 index 0000000..6d4dfcf --- /dev/null +++ b/include/configs/socfpga_common.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_COMMON_H +#define __CONFIG_COMMON_H + +#include <asm/arch/socfpga_base_addrs.h> +#include "../../board/altera/socfpga/pinmux_config.h" + +/* + * High level configuration + */ +/* Virtual target or real hardware */ +#define CONFIG_SOCFPGA_VIRTUAL_TARGET + +#define CONFIG_ARMV7 +#define CONFIG_L2_OFF +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_USE_IRQ + +#define CONFIG_MISC_INIT_R +#define CONFIG_SINGLE_BOOTLOADER +#define CONFIG_SOCFPGA + +/* base address for .text section */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TEXT_BASE 0x08000040 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 +#endif +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Enable early stage initialization at C environment + */ +#define CONFIG_BOARD_EARLY_INIT_F + +/* flat device tree */ +#define CONFIG_OF_LIBFDT +/* skip updating the FDT blob */ +#define CONFIG_FDT_BLOB_SKIP_UPDATE +/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ +#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) +#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) + +/* + * Memory allocation (MALLOC) + */ +/* Room required on the stack for the environment data */ +#define CONFIG_ENV_SIZE 1024 +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) + +/* SP location before relocation, must use scratch RAM */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +/* Reserving 0x100 space at back of scratch RAM for debug info */ +#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + + +/* + * Command line configuration. + */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +/* FAT file system support */ +#define CONFIG_CMD_FAT + + +/* + * Misc + */ +#define CONFIG_DOS_PARTITION 1 + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_PARTITIONS +#endif + +/* + * Environment setup + */ + +/* Delay before automatically booting the default image */ +#define CONFIG_BOOTDELAY 3 +/* Enable auto completion of commands using TAB */ +#define CONFIG_AUTO_COMPLETE +/* use "hush" command parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMD_RUN + +#define CONFIG_BOOTCOMMAND "run ramboot" + +/* + * arguments passed to the bootm command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=uImage\0" \ + "fdt_addr=100\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* using environment setting for stdin, stdout, stderr */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* Enable the call to overwrite_console() */ +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +/* Enable overwrite of previous console environment settings */ +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + + +/* + * Hardware drivers + */ + +/* + * SDRAM Memory Map + */ +/* We have 1 bank of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +/* SDRAM Bank #1 */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +/* SDRAM memory size */ +#define PHYS_SDRAM_1_SIZE 0x40000000 + +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE + +/* + * NS16550 Configuration + */ +#define UART0_BASE SOCFPGA_UART0_ADDRESS +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART0_BASE +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define V_NS16550_CLK 1000000 +#else +#define V_NS16550_CLK 100000000 +#endif +#define CONFIG_BAUDRATE 115200 + +/* + * FLASH + */ +#define CONFIG_SYS_NO_FLASH + +/* + * L4 OSC1 Timer 0 + */ +/* This timer use eosc1 where the clock frequency is fixed + * throughout any condition */ +#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF +/* Timer info */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_SYS_TIMER_RATE 2400000 +#else +#define CONFIG_SYS_TIMER_RATE 25000000 +#endif +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) + +#define CONFIG_ENV_IS_NOWHERE + +/* + * SPL "Second Program Loader" aka Initial Software + */ + +/* Enable building of SPL globally */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK + +/* TEXT_BASE for linking the SPL binary */ +#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 + +/* Stack size for SPL */ +#define CONFIG_SPL_STACK_SIZE (4 * 1024) + +/* MALLOC size for SPL */ +#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CHUNKSZ_CRC32 (1 * 1024) + +#define CONFIG_CRC32_VERIFY + +/* Linker script for SPL */ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" + +/* Support for common/libcommon.o in SPL binary */ +#define CONFIG_SPL_LIBCOMMON_SUPPORT +/* Support for lib/libgeneric.o in SPL binary */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#endif /* __CONFIG_COMMON_H */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 980636c..87de4d2 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -6,235 +6,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include <asm/arch/socfpga_base_addrs.h> -#include "../../board/altera/socfpga/pinmux_config.h" +#include <configs/socfpga_common.h> -/* - * High level configuration - */ -/* Virtual target or real hardware */ -#define CONFIG_SOCFPGA_VIRTUAL_TARGET - -#define CONFIG_ARMV7 -#define CONFIG_L2_OFF -#define CONFIG_SYS_DCACHE_OFF -#undef CONFIG_USE_IRQ - -#define CONFIG_MISC_INIT_R -#define CONFIG_SINGLE_BOOTLOADER -#define CONFIG_SOCFPGA - -/* base address for .text section */ #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TEXT_BASE 0x08000040 +#define ALTERA_BOARD_NAME "Altera VTDEV5XS1 Virtual Board" #else -#define CONFIG_SYS_TEXT_BASE 0x01000040 -#endif -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # " -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * Display CPU and Board Info - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* - * Enable early stage initialization at C environment - */ -#define CONFIG_BOARD_EARLY_INIT_F - -/* flat device tree */ -#define CONFIG_OF_LIBFDT -/* skip updating the FDT blob */ -#define CONFIG_FDT_BLOB_SKIP_UPDATE -/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */ -#define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024)) - -#define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start)) -#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start) - -/* - * Memory allocation (MALLOC) - */ -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE 1024 -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* SP location before relocation, must use scratch RAM */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -/* Reserving 0x100 space at back of scratch RAM for debug info */ -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100) -/* Stack pointer prior relocation, must situated at on-chip RAM */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - - -/* - * Command line configuration. - */ -#define CONFIG_SYS_NO_FLASH -#include <config_cmd_default.h> -/* FAT file system support */ -#define CONFIG_CMD_FAT - - -/* - * Misc - */ -#define CONFIG_DOS_PARTITION 1 - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_PARTITIONS +#define ALTERA_BOARD_NAME "Altera SOCFPGA Cyclone 5 Board" #endif -/* - * Environment setup - */ - -/* Delay before automatically booting the default image */ -#define CONFIG_BOOTDELAY 3 -/* Enable auto completion of commands using TAB */ -#define CONFIG_AUTO_COMPLETE -/* use "hush" command parser */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_CMD_RUN - -#define CONFIG_BOOTCOMMAND "run ramboot" - -/* - * arguments passed to the bootm command. The value of - * CONFIG_BOOTARGS goes into the environment value "bootargs". - * Do note the value will overide also the chosen node in FDT blob. - */ -#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "bootimage=uImage\0" \ - "fdt_addr=100\0" \ - "fsloadcmd=ext2load\0" \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "qspiroot=/dev/mtdblock0\0" \ - "qspirootfstype=jffs2\0" \ - "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ - "bootm ${loadaddr} - ${fdt_addr}\0" - -/* using environment setting for stdin, stdout, stderr */ -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -/* Enable the call to overwrite_console() */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -/* Enable overwrite of previous console environment settings */ -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - - -/* - * Hardware drivers - */ - -/* - * SDRAM Memory Map - */ -/* We have 1 bank of DRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -/* SDRAM Bank #1 */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -/* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x40000000 - -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - -/* - * NS16550 Configuration - */ -#define UART0_BASE SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define V_NS16550_CLK 1000000 -#else -#define V_NS16550_CLK 100000000 -#endif -#define CONFIG_BAUDRATE 115200 - -/* - * FLASH - */ -#define CONFIG_SYS_NO_FLASH - -/* - * L4 OSC1 Timer 0 - */ -/* This timer use eosc1 where the clock frequency is fixed - * throughout any condition */ -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0xFFFFFFFF -/* Timer info */ -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TIMER_RATE 2400000 -#else -#define CONFIG_SYS_TIMER_RATE 25000000 -#endif -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) - -#define CONFIG_ENV_IS_NOWHERE - -/* - * SPL "Second Program Loader" aka Initial Software - */ - -/* Enable building of SPL globally */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK - -/* TEXT_BASE for linking the SPL binary */ -#define CONFIG_SPL_TEXT_BASE 0xFFFF0000 - -/* Stack size for SPL */ -#define CONFIG_SPL_STACK_SIZE (4 * 1024) - -/* MALLOC size for SPL */ -#define CONFIG_SPL_MALLOC_SIZE (5 * 1024) - -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_BOARD_INIT - -#define CHUNKSZ_CRC32 (1 * 1024) - -#define CONFIG_CRC32_VERIFY - -/* Linker script for SPL */ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds" - -/* Support for common/libcommon.o in SPL binary */ -#define CONFIG_SPL_LIBCOMMON_SUPPORT -/* Support for lib/libgeneric.o in SPL binary */ -#define CONFIG_SPL_LIBGENERIC_SUPPORT - #endif /* __CONFIG_H */ diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h new file mode 100644 index 0000000..2f1c3a4 --- /dev/null +++ b/include/configs/socfpga_socrates.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/socfpga_common.h> + +#define ALTERA_BOARD_NAME "EBV SoCrates - Cyclone V SoC FPGA Board" + +#endif /* __CONFIG_H */
Altera Cyclone 5 board is very different board (big, rectangular, expensive) than EBV Socrates (small, circular, cheap) board. Different parts are used there, too, but same configuration of u-boot works on both. Nevertheless, printing wrong name confuses users. Therefore this splits the configuration so that u-boot knows they are different. So far it is only used for correcting the puts, but there may be other uses in future. Signed-off-by: Pavel Machek <pavel@denx.de>