diff mbox

[U-Boot,v2,01/19] Makefile: prepare for using Kbuild-style Makefile

Message ID 1380196286-10810-2-git-send-email-yamada.m@jp.panasonic.com
State Superseded
Delegated to: Tom Rini
Headers show

Commit Message

Masahiro Yamada Sept. 26, 2013, 11:51 a.m. UTC 
In every sub directory, Makefile is like follows:

    include $(TOPDIR)/config.mk

    LIB     = $(obj)libfoo.o

    COBJS := ...
    COBJS += ...
    SOBJS := ...

    SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
    OBJS    := $(addprefix $(obj),$(COBJS) $(SOBJS))

    all:     $(obj).depend $(LIB)

    $(LIB): $(OBJS)
            $(call cmd_link_o_target, $(OBJS))

    #########################################################################

    include $(SRCTREE)/rules.mk

    sinclude $(obj).depend

    #########################################################################

Top and bottom parts are common in almost all sub-makefiles.
This is a big waste.
This commit pushes common parts of makefiles into script/Makefile.build.

Going forward sub-makefiles only need to describe this part:

    COBJS := ...
    COBJS += ...
    SOBJS := ...

But, script/Makefile.build includes the glue code to support obj-y,
the following style (the same as Kbuild) is preferable:

    obj-y := ...
    obj-$(CONFIG_FOO) += ...
    obj-$(CONFIG_BAR) += ...

The conventional (non-Kbuild) Makefile style is still supported.
This is achieved by greping the Makefile before entering into it.
U-Boot conventional sub makefiles always include some other makefiles.
So the build system searches a line beginning with "include" keyword
in the makefile in order to distinguish which style it is.
If the Makefile include a "include" line, we assume it is a conventional
U-Boot style. Otherwise, it is treated as a Kbuild-style makefile.

(At first, I tried to grep "rules.mk" keyword instead,
but I found it does not work.
Almost all sub makefiles include "rules.mk", but there exist three exception:
   - board/avnet/fx12mm/Makefile
   - board/avnet/v5fx30teval/Makefile
   - board/xilinx/ml507/Makefile
These three makefiles include "rules.mk" indirectly.
Anyway, they look weird, so they should be fixed lator.)

With this tweak, we can switch sub-makefiles
from U-Boot style to Kbuild style little by little.

This refactoring of sub makefiles is the first step towards Kbuild,
and makes it easy to import a "real" Kbuild from Linux Kernel.

Note that this refactoring breaks nothing because it just moves
the common parts into scripts/Makefile.build.

Note one more thing:

    obj-y := foo/  # descending into foo sub directory

syntax is not supported yet.
(This feature will be implemented in the upcoming commit.)

Of course, scripts/Makefile.build added by this commit is temporary.
It shall be replaced with the one of Linux Kernel in future.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
---

Changes for v2:
  - fix commit log (purely cosmetic)

 Makefile               | 34 ++++++++++++++++++++++++++++++----
 scripts/Makefile.build | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 spl/Makefile           | 20 ++++++++++++++++++--
 3 files changed, 96 insertions(+), 6 deletions(-)
 create mode 100644 scripts/Makefile.build

Comments

Simon Glass Oct. 3, 2013, 11:38 p.m. UTC | #1 
Hi,

On Thu, Sep 26, 2013 at 5:51 AM, Masahiro Yamada
<yamada.m@jp.panasonic.com>wrote:

> In every sub directory, Makefile is like follows:
>
>     include $(TOPDIR)/config.mk
>
>     LIB     = $(obj)libfoo.o
>
>     COBJS := ...
>     COBJS += ...
>     SOBJS := ...
>
>     SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
>     OBJS    := $(addprefix $(obj),$(COBJS) $(SOBJS))
>
>     all:     $(obj).depend $(LIB)
>
>     $(LIB): $(OBJS)
>             $(call cmd_link_o_target, $(OBJS))
>
>
> #########################################################################
>
>     include $(SRCTREE)/rules.mk
>
>     sinclude $(obj).depend
>
>
> #########################################################################
>
> Top and bottom parts are common in almost all sub-makefiles.
> This is a big waste.
> This commit pushes common parts of makefiles into script/Makefile.build.
>
> Going forward sub-makefiles only need to describe this part:
>
>     COBJS := ...
>     COBJS += ...
>     SOBJS := ...
>
> But, script/Makefile.build includes the glue code to support obj-y,
> the following style (the same as Kbuild) is preferable:
>
>     obj-y := ...
>     obj-$(CONFIG_FOO) += ...
>     obj-$(CONFIG_BAR) += ...
>
> The conventional (non-Kbuild) Makefile style is still supported.
> This is achieved by greping the Makefile before entering into it.
> U-Boot conventional sub makefiles always include some other makefiles.
> So the build system searches a line beginning with "include" keyword
> in the makefile in order to distinguish which style it is.
> If the Makefile include a "include" line, we assume it is a conventional
> U-Boot style. Otherwise, it is treated as a Kbuild-style makefile.
>
> (At first, I tried to grep "rules.mk" keyword instead,
> but I found it does not work.
> Almost all sub makefiles include "rules.mk", but there exist three
> exception:
>    - board/avnet/fx12mm/Makefile
>    - board/avnet/v5fx30teval/Makefile
>    - board/xilinx/ml507/Makefile
> These three makefiles include "rules.mk" indirectly.
> Anyway, they look weird, so they should be fixed lator.)
>
> With this tweak, we can switch sub-makefiles
> from U-Boot style to Kbuild style little by little.
>
> This refactoring of sub makefiles is the first step towards Kbuild,
> and makes it easy to import a "real" Kbuild from Linux Kernel.
>
> Note that this refactoring breaks nothing because it just moves
> the common parts into scripts/Makefile.build.
>
> Note one more thing:
>
>     obj-y := foo/  # descending into foo sub directory
>
> syntax is not supported yet.
> (This feature will be implemented in the upcoming commit.)
>
> Of course, scripts/Makefile.build added by this commit is temporary.
> It shall be replaced with the one of Linux Kernel in future.
>
> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Tom Rini <trini@ti.com>
> ---
>
> Changes for v2:
>   - fix commit log (purely cosmetic)
>
>  Makefile               | 34 ++++++++++++++++++++++++++++++----
>  scripts/Makefile.build | 48
> ++++++++++++++++++++++++++++++++++++++++++++++++
>  spl/Makefile           | 20 ++++++++++++++++++--
>  3 files changed, 96 insertions(+), 6 deletions(-)
>  create mode 100644 scripts/Makefile.build
>
> diff --git a/Makefile b/Makefile
> index 07abef4..36bbd09 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -593,14 +593,35 @@ ifeq ($(CONFIG_KALLSYMS),y)
>                 $(GEN_UBOOT) $(obj)common/system_map.o
>  endif
>
> +# Tentative step for Kbuild-style makefiles coexist with conventional
> U-Boot style makefiles
> +#  U-Boot conventional sub makefiles always include some other makefiles.
> +#  So, the build system searches a line beginning with "include" before
> entering into the sub makefile
> +#  in order to distinguish which style it is.
>

Would looking for obj- be better or worse?


> +#  If the Makefile include a "include" line, we assume it is an U-Boot
> style makefile.
> +#  Otherwise, it is treated as a Kbuild-style makefile.
> +
> +# We do not need to build $(OBJS) explicitly.
> +# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
>  $(OBJS):       depend
> -               $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
> +               if grep -q "^include" $(CPUDIR)/Makefile; then \
> +               $(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir
> $@)); \
>

an indent might help here, and below.


> +               fi
>
>  $(LIBS):       depend $(SUBDIR_TOOLS)
> -               $(MAKE) -C $(dir $(subst $(obj),,$@))
> +               if grep -q "^include" $(dir $(subst $(obj),,$@))Makefile;
> then \
>

This check seems to appear a lot - could it become a $(call ...) perhaps?


> +               $(MAKE) -C $(dir $(subst $(obj),,$@)); \
> +               else \
> +               $(MAKE) -C $(dir $(subst $(obj),,$@)) -f
> $(TOPDIR)/scripts/Makefile.build; \
> +               mv $(dir $@)built-in.o $@; \
> +               fi
>
>  $(LIBBOARD):   depend $(LIBS)
> -               $(MAKE) -C $(dir $(subst $(obj),,$@))
> +               if grep -q "^include" $(dir $(subst $(obj),,$@))/Makefile;
> then \
> +               $(MAKE) -C $(dir $(subst $(obj),,$@)); \
> +               else \
> +               $(MAKE) -C $(dir $(subst $(obj),,$@)) -f
> $(TOPDIR)/scripts/Makefile.build; \
> +               mv $(dir $@)built-in.o $@; \
> +               fi
>
>  $(SUBDIRS):    depend
>                 $(MAKE) -C $@ all
> @@ -637,7 +658,12 @@ depend dep:        $(TIMESTAMP_FILE) $(VERSION_FILE) \
>                 $(obj)include/generated/generic-asm-offsets.h \
>                 $(obj)include/generated/asm-offsets.h
>                 for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ;
> do \
> -                       $(MAKE) -C $$dir _depend ; done
> +               if grep -q "^include" $$dir/Makefile; then \
> +                       $(MAKE) -C $$dir _depend ; \
> +               else \
> +                       $(MAKE) -C $$dir -f
> $(TOPDIR)/scripts/Makefile.build _depend; \
> +               fi; \
> +               done
>
>  TAG_SUBDIRS = $(SUBDIRS)
>  TAG_SUBDIRS += $(dir $(__LIBS))
> diff --git a/scripts/Makefile.build b/scripts/Makefile.build
> new file mode 100644
> index 0000000..f969ec5
> --- /dev/null
> +++ b/scripts/Makefile.build
> @@ -0,0 +1,48 @@
> +# our default target
> +.PHONY: all
> +all:
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB := $(obj)built-in.o
> +LIBGCC = $(obj)libgcc.o
> +SRCS :=
> +
> +include Makefile
> +
> +# Backward compatible: obj-y is preferable
> +COBJS := $(sort $(COBJS) $(COBJS-y))
> +SOBJS := $(sort $(SOBJS) $(SOBJS-y))
> +
> +# Going forward use the following
> +obj-y := $(sort $(obj-y))
> +extra-y := $(sort $(extra-y))
> +lib-y := $(sort $(lib-y))
> +
> +SRCS   += $(COBJS:.o=.c) $(SOBJS:.o=.S) \
> + $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S)
> $(extra-y:.o=.c) $(extra-y:.o=.S))
> +OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y))
> +
> +LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y))
> +
> +all: $(LIB) $(addprefix $(obj),$(extra-y))
> +
> +$(LIB):        $(obj).depend $(OBJS)
> +       $(call cmd_link_o_target, $(OBJS))
> +
> +ifneq ($(strip $(lib-y)),)
> +all: $(LIBGCC)
> +
> +$(LIBGCC): $(obj).depend $(LGOBJS)
> +       $(call cmd_link_o_target, $(LGOBJS))
> +endif
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +
> +include $(TOPDIR)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/spl/Makefile b/spl/Makefile
> index 174d0a7..48f2c65 100644
> --- a/spl/Makefile
> +++ b/spl/Makefile
> @@ -199,11 +199,27 @@ GEN_UBOOT = \
>  $(obj)$(SPL_BIN):      depend $(START) $(LIBS) $(obj)u-boot-spl.lds
>         $(GEN_UBOOT)
>
> +# Tentative step for Kbuild-style makefiles coexist with conventional
> U-Boot style makefiles
> +#  U-Boot conventional sub makefiles always include some other makefiles.
> +#  So, the build system searches a line beginning with "include" before
> entering into the sub makefile
> +#  in order to distinguish which style it is.
> +#  If the Makefile include a "include" line, we assume it is an U-Boot
> style makefile.
> +#  Otherwise, it is treated as a Kbuild-style makefile.
> +
> +# We do not need to build $(START) explicitly.
> +# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
>  $(START):      depend
> -       $(MAKE) -C $(SRCTREE)/$(START_PATH) $@
> +       if grep -q "^include" $(SRCTREE)$(dir $(subst
> $(SPLTREE),,$@))Makefile; then \
> +       $(MAKE) -C $(SRCTREE)/$(START_PATH) $@; \
> +       fi
>
>  $(LIBS):       depend
> -       $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
> +       if grep -q "^include" $(SRCTREE)$(dir $(subst
> $(SPLTREE),,$@))Makefile; then \
> +       $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)); \
> +       else \
> +       $(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) -f
> $(TOPDIR)/scripts/Makefile.build; \
> +       mv $(dir $@)built-in.o $@; \
> +       fi
>
>  $(obj)u-boot-spl.lds: $(LDSCRIPT) depend
>         $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P
> - < $< > $@
> --
> 1.8.1.2
>
>
Re testing, I used:

$ ./tools/buildman/buildman -b try-kbuild -k

and confirmed that the binaries do change, for example, with cm41xx:

$ wc ...
   1348    5418  123176
try-kbuild/01_of_20_g0c5274e6_Prepare-v2013.04-rc4/cm41xx/u-boot.bin
   1348    5417  123188
try-kbuild/02_of_20_gd3068182_Makefile--prepare-fo/cm41xx/u-boot.bin

The change may well be harmless though.

It would be nice to add a feature to buildman to compare binaries. Of
course we would need to add a Makefile option to disable the timestamp
embedding first, since all binaries are different because of that.

Regards,
Simon
Masahiro Yamada Oct. 4, 2013, 9:59 a.m. UTC | #2 
Hello Simon



> > +# Tentative step for Kbuild-style makefiles coexist with conventional
> > U-Boot style makefiles
> > +#  U-Boot conventional sub makefiles always include some other makefiles.
> > +#  So, the build system searches a line beginning with "include" before
> > entering into the sub makefile
> > +#  in order to distinguish which style it is.
> >
> 
> Would looking for obj- be better or worse?

At first I thought of this but I was kind of worried
whether all makefiles should forcibly have obj-y or obj-.

arch/arm/cpu/armv7/tegra114/
arch/arm/cpu/armv7/tegra30/
directories have no source files but only a Makefile.

After all, I simply added
obj- :=
line in them, so I think your suggestion will work.

If you prefer to search obj-, I will consider to change at version 3.

In any case, this ugly grep switch is tentative.
I want to refactor all makefiles and delete this switch
as soon as possible.



> an indent might help here, and below.

I will fix at v3.



> > +               fi
> >
> >  $(LIBS):       depend $(SUBDIR_TOOLS)
> > -               $(MAKE) -C $(dir $(subst $(obj),,$@))
> > +               if grep -q "^include" $(dir $(subst $(obj),,$@))Makefile;
> > then \
> >
> 
> This check seems to appear a lot - could it become a $(call ...) perhaps?


I did not care so much about this part becuase it is temporary.
But re-writing it shortly with $(call ...) is not difficult.
I will try at v3.
Thanks for your advice.




> Re testing, I used:
> 
> $ ./tools/buildman/buildman -b try-kbuild -k
> 
> and confirmed that the binaries do change, for example, with cm41xx:
> 
> $ wc ...
>    1348    5418  123176
> try-kbuild/01_of_20_g0c5274e6_Prepare-v2013.04-rc4/cm41xx/u-boot.bin
>    1348    5417  123188
> try-kbuild/02_of_20_gd3068182_Makefile--prepare-fo/cm41xx/u-boot.bin
> 
> The change may well be harmless though.

It is probably because of include/generated/version_autogenerated.h

The length of PLAIN_VERSION and U_BOOT_VERSION changes
because the output `git describe` command is used for here.

Actually I gave it a try.


For master branch (Prepare v2013.04-rc4), I got:

#define PLAIN_VERSION "2013.10-rc4"
#define U_BOOT_VERSION "U-Boot 2013.10-rc4"
#define CC_VERSION_STRING "arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-1ubuntu1) 4.7.3"
#define LD_VERSION_STRING "GNU ld (GNU Binutils for Ubuntu) 2.23.2"


For try-kbuild branch (Makefile: prepare for using Kbuild-style Makefile)
I got:

#define PLAIN_VERSION "2013.10-rc4-00001-gc31a399"
#define U_BOOT_VERSION "U-Boot 2013.10-rc4-00001-gc31a399"
#define CC_VERSION_STRING "arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-1ubuntu1) 4.7.3"
#define LD_VERSION_STRING "GNU ld (GNU Binutils for Ubuntu) 2.23.2"


For the list of things you should take into account to get identical
output files, please refer the thread of version1 of this series:
[U-Boot] [PATCH 00/19] First step towards Kbuild: Use Kbuild style makefiles
Message-Id: <20130917093533.738A.AA925319@jp.panasonic.com>


> (2) Git commit hash
> 
> Git commit hash is contained in include/generated/version_autogenerated.h.
> So, I also modified include/version.h not to include it as follows:
> 
>      #ifndef DO_DEPS_ONLY
>     -#include "generated/version_autogenerated.h"
>     +/* #include "generated/version_autogenerated.h" */
>     +#define PLAIN_VERSION "__DUMMY__"
>     +#define U_BOOT_VERSION "__DUMMY__"
>     +#define CC_VERSION_STRING "__DUMMY__"
>     +#define LD_VERSION_STRING "__DUMMY__"
>      #endif

This is what I did when I compared md5sum.
After applying above as a prerequisite commit,
I tried 'tools/buildman/buildman -b try-kbuild -k' again
and I got the same size for cm41xx/u-boot.bin


If you compare the size of u-boot.bin,
please take care of the order of object files too.

I also mentioned this in the thread of v1.





> It would be nice to add a feature to buildman to compare binaries. Of
> course we would need to add a Makefile option to disable the timestamp
> embedding first, since all binaries are different because of that.

Sounds a good idea.
I will take a look when I have time.



Best Regards
Masahiro Yamada
Simon Glass Oct. 4, 2013, 3:38 p.m. UTC | #3 
Hi Masahiro,

On Fri, Oct 4, 2013 at 3:59 AM, Masahiro Yamada
<yamada.m@jp.panasonic.com> wrote:
> Hello Simon
>
>
>
>> > +# Tentative step for Kbuild-style makefiles coexist with conventional
>> > U-Boot style makefiles
>> > +#  U-Boot conventional sub makefiles always include some other makefiles.
>> > +#  So, the build system searches a line beginning with "include" before
>> > entering into the sub makefile
>> > +#  in order to distinguish which style it is.
>> >
>>
>> Would looking for obj- be better or worse?
>
> At first I thought of this but I was kind of worried
> whether all makefiles should forcibly have obj-y or obj-.
>
> arch/arm/cpu/armv7/tegra114/
> arch/arm/cpu/armv7/tegra30/
> directories have no source files but only a Makefile.
>
> After all, I simply added
> obj- :=
> line in them, so I think your suggestion will work.
>
> If you prefer to search obj-, I will consider to change at version 3.

No, it doesn't matter, it sounds like what you are doing is just as
good, and it is temporary as you say. I wonder how temporary?

>
> In any case, this ugly grep switch is tentative.
> I want to refactor all makefiles and delete this switch
> as soon as possible.
>
>
>
>> an indent might help here, and below.
>
> I will fix at v3.
>
>
>
>> > +               fi
>> >
>> >  $(LIBS):       depend $(SUBDIR_TOOLS)
>> > -               $(MAKE) -C $(dir $(subst $(obj),,$@))
>> > +               if grep -q "^include" $(dir $(subst $(obj),,$@))Makefile;
>> > then \
>> >
>>
>> This check seems to appear a lot - could it become a $(call ...) perhaps?
>
>
> I did not care so much about this part becuase it is temporary.
> But re-writing it shortly with $(call ...) is not difficult.
> I will try at v3.
> Thanks for your advice.
>
>
>
>
>> Re testing, I used:
>>
>> $ ./tools/buildman/buildman -b try-kbuild -k
>>
>> and confirmed that the binaries do change, for example, with cm41xx:
>>
>> $ wc ...
>>    1348    5418 123176
>> try-kbuild/01_of_20_g0c5274e6_Prepare-v2013.04-rc4/cm41xx/u-boot.bin
>>    1348    5417  123188
>> try-kbuild/02_of_20_gd3068182_Makefile--prepare-fo/cm41xx/u-boot.bin
>>
>> The change may well be harmless though.
>
> It is probably because of include/generated/version_autogenerated.h
>
> The length of PLAIN_VERSION and U_BOOT_VERSION changes
> because the output `git describe` command is used for here.
>
> Actually I gave it a try.
>
>
> For master branch (Prepare v2013.04-rc4), I got:
>
> #define PLAIN_VERSION "2013.10-rc4"
> #define U_BOOT_VERSION "U-Boot 2013.10-rc4"
> #define CC_VERSION_STRING "arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-1ubuntu1) 4.7.3"
> #define LD_VERSION_STRING "GNU ld (GNU Binutils for Ubuntu) 2.23.2"
>
>
> For try-kbuild branch (Makefile: prepare for using Kbuild-style Makefile)
> I got:
>
> #define PLAIN_VERSION "2013.10-rc4-00001-gc31a399"
> #define U_BOOT_VERSION "U-Boot 2013.10-rc4-00001-gc31a399"
> #define CC_VERSION_STRING "arm-linux-gnueabi-gcc (Ubuntu/Linaro 4.7.3-1ubuntu1) 4.7.3"
> #define LD_VERSION_STRING "GNU ld (GNU Binutils for Ubuntu) 2.23.2"
>
>
> For the list of things you should take into account to get identical
> output files, please refer the thread of version1 of this series:
> [U-Boot] [PATCH 00/19] First step towards Kbuild: Use Kbuild style makefiles
> Message-Id: <20130917093533.738A.AA925319@jp.panasonic.com>
>
>
>> (2) Git commit hash
>>
>> Git commit hash is contained in include/generated/version_autogenerated.h.
>> So, I also modified include/version.h not to include it as follows:
>>
>>      #ifndef DO_DEPS_ONLY
>>     -#include "generated/version_autogenerated.h"
>>     +/* #include "generated/version_autogenerated.h" */
>>     +#define PLAIN_VERSION "__DUMMY__"
>>     +#define U_BOOT_VERSION "__DUMMY__"
>>     +#define CC_VERSION_STRING "__DUMMY__"
>>     +#define LD_VERSION_STRING "__DUMMY__"
>>      #endif
>
> This is what I did when I compared md5sum.
> After applying above as a prerequisite commit,
> I tried 'tools/buildman/buildman -b try-kbuild -k' again
> and I got the same size for cm41xx/u-boot.bin
>
>
> If you compare the size of u-boot.bin,
> please take care of the order of object files too.
>
> I also mentioned this in the thread of v1.
>
>
>
>
>
>> It would be nice to add a feature to buildman to compare binaries. Of
>> course we would need to add a Makefile option to disable the timestamp
>> embedding first, since all binaries are different because of that.
>
> Sounds a good idea.
> I will take a look when I have time.
>
>

Regards,
Simon
Masahiro Yamada Oct. 21, 2013, 4:56 a.m. UTC | #4 
Hello, Simon.


> >> Would looking for obj- be better or worse?
> >
> > At first I thought of this but I was kind of worried
> > whether all makefiles should forcibly have obj-y or obj-.
> >
> > arch/arm/cpu/armv7/tegra114/
> > arch/arm/cpu/armv7/tegra30/
> > directories have no source files but only a Makefile.
> >
> > After all, I simply added
> > obj- :=
> > line in them, so I think your suggestion will work.
> >
> > If you prefer to search obj-, I will consider to change at version 3.
> 
> No, it doesn't matter, it sounds like what you are doing is just as
> good, and it is temporary as you say. I wonder how temporary?


I posted a new series
"Third step towards Kbuild: Convert rest of makefiles" (consists of 18 patch files)
The series deletes the temporary grep switch.

Altough it is Tom who decides when the series should be applied,
I hope it is not so late.


Best Regards
Masahiro Yamada
Simon Glass Oct. 21, 2013, 10:01 p.m. UTC | #5 
Hi Masahiro,

On Sun, Oct 20, 2013 at 10:56 PM, Masahiro Yamada
<yamada.m@jp.panasonic.com> wrote:
> Hello, Simon.
>
>
>> >> Would looking for obj- be better or worse?
>> >
>> > At first I thought of this but I was kind of worried
>> > whether all makefiles should forcibly have obj-y or obj-.
>> >
>> > arch/arm/cpu/armv7/tegra114/
>> > arch/arm/cpu/armv7/tegra30/
>> > directories have no source files but only a Makefile.
>> >
>> > After all, I simply added
>> > obj- :=
>> > line in them, so I think your suggestion will work.
>> >
>> > If you prefer to search obj-, I will consider to change at version 3.
>>
>> No, it doesn't matter, it sounds like what you are doing is just as
>> good, and it is temporary as you say. I wonder how temporary?
>
>
> I posted a new series
> "Third step towards Kbuild: Convert rest of makefiles" (consists of 18 patch files)
> The series deletes the temporary grep switch.
>
> Altough it is Tom who decides when the series should be applied,
> I hope it is not so late.

The merge window only opened recently so it should be fine.

Regards,
Simon


>
>
> Best Regards
> Masahiro Yamada
>
diff mbox

Patch

diff --git a/Makefile b/Makefile
index 07abef4..36bbd09 100644
--- a/Makefile
+++ b/Makefile
@@ -593,14 +593,35 @@  ifeq ($(CONFIG_KALLSYMS),y)
 		$(GEN_UBOOT) $(obj)common/system_map.o
 endif
 
+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
+#  U-Boot conventional sub makefiles always include some other makefiles.
+#  So, the build system searches a line beginning with "include" before entering into the sub makefile
+#  in order to distinguish which style it is.
+#  If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
+#  Otherwise, it is treated as a Kbuild-style makefile.
+
+# We do not need to build $(OBJS) explicitly.
+# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
 $(OBJS):	depend
-		$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
+		if grep -q "^include" $(CPUDIR)/Makefile; then \
+		$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)); \
+		fi
 
 $(LIBS):	depend $(SUBDIR_TOOLS)
-		$(MAKE) -C $(dir $(subst $(obj),,$@))
+		if grep -q "^include" $(dir $(subst $(obj),,$@))Makefile; then \
+		$(MAKE) -C $(dir $(subst $(obj),,$@)); \
+		else \
+		$(MAKE) -C $(dir $(subst $(obj),,$@)) -f $(TOPDIR)/scripts/Makefile.build; \
+		mv $(dir $@)built-in.o $@; \
+		fi
 
 $(LIBBOARD):	depend $(LIBS)
-		$(MAKE) -C $(dir $(subst $(obj),,$@))
+		if grep -q "^include" $(dir $(subst $(obj),,$@))/Makefile; then \
+		$(MAKE) -C $(dir $(subst $(obj),,$@)); \
+		else \
+		$(MAKE) -C $(dir $(subst $(obj),,$@)) -f $(TOPDIR)/scripts/Makefile.build; \
+		mv $(dir $@)built-in.o $@; \
+		fi
 
 $(SUBDIRS):	depend
 		$(MAKE) -C $@ all
@@ -637,7 +658,12 @@  depend dep:	$(TIMESTAMP_FILE) $(VERSION_FILE) \
 		$(obj)include/generated/generic-asm-offsets.h \
 		$(obj)include/generated/asm-offsets.h
 		for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
-			$(MAKE) -C $$dir _depend ; done
+		if grep -q "^include" $$dir/Makefile; then \
+			$(MAKE) -C $$dir _depend ; \
+		else \
+			$(MAKE) -C $$dir -f $(TOPDIR)/scripts/Makefile.build _depend; \
+		fi; \
+		done
 
 TAG_SUBDIRS = $(SUBDIRS)
 TAG_SUBDIRS += $(dir $(__LIBS))
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
new file mode 100644
index 0000000..f969ec5
--- /dev/null
+++ b/scripts/Makefile.build
@@ -0,0 +1,48 @@ 
+# our default target
+.PHONY: all
+all:
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)built-in.o
+LIBGCC = $(obj)libgcc.o
+SRCS :=
+
+include Makefile
+
+# Backward compatible: obj-y is preferable
+COBJS := $(sort $(COBJS) $(COBJS-y))
+SOBJS := $(sort $(SOBJS) $(SOBJS-y))
+
+# Going forward use the following
+obj-y := $(sort $(obj-y))
+extra-y := $(sort $(extra-y))
+lib-y := $(sort $(lib-y))
+
+SRCS	+= $(COBJS:.o=.c) $(SOBJS:.o=.S) \
+ $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S))
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y))
+
+LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y))
+
+all: $(LIB) $(addprefix $(obj),$(extra-y))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+ifneq ($(strip $(lib-y)),)
+all: $(LIBGCC)
+
+$(LIBGCC): $(obj).depend $(LGOBJS)
+	$(call cmd_link_o_target, $(LGOBJS))
+endif
+
+#########################################################################
+
+# defines $(obj).depend target
+
+include $(TOPDIR)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/spl/Makefile b/spl/Makefile
index 174d0a7..48f2c65 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -199,11 +199,27 @@  GEN_UBOOT = \
 $(obj)$(SPL_BIN):	depend $(START) $(LIBS) $(obj)u-boot-spl.lds
 	$(GEN_UBOOT)
 
+# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
+#  U-Boot conventional sub makefiles always include some other makefiles.
+#  So, the build system searches a line beginning with "include" before entering into the sub makefile
+#  in order to distinguish which style it is.
+#  If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
+#  Otherwise, it is treated as a Kbuild-style makefile.
+
+# We do not need to build $(START) explicitly.
+# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
 $(START):	depend
-	$(MAKE) -C $(SRCTREE)/$(START_PATH) $@
+	if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \
+	$(MAKE) -C $(SRCTREE)/$(START_PATH) $@; \
+	fi
 
 $(LIBS):	depend
-	$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
+	if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \
+	$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)); \
+	else \
+	$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) -f $(TOPDIR)/scripts/Makefile.build; \
+	mv $(dir $@)built-in.o $@; \
+	fi
 
 $(obj)u-boot-spl.lds: $(LDSCRIPT) depend
 	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@