| Message ID | 1361394350-16585-4-git-send-email-twarren@nvidia.com |
|---|---|
| State | Superseded |
| Delegated to: | Tom Warren |
| Headers | show |
On 02/20/2013 02:05 PM, Tom Warren wrote: > Linux dts files were used for those boards that didn't already > have sdhci info populated. Tamonten has their own dtsi file with > common sdhci nodes (sourced from Linux). So this patch now does a two unrelated things: a) Switches from /include/ to #include. b) A bunch of changes for the SDHCI properties. Those should really be separate patches. > diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts > -/include/ ARCH_CPU_DTS > +#include ARCH_CPU_DTS I think we should get rid of ARCH_CPU_DTS too. The only reason it ever existed was because we were using dtc's include processing and had to work around some issue with that (I can't remember exactly what, but Simon will). Now that we're using cpp's include processing, we can simply write: #include "tegra20.dtsi". > diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts > /memreserve/ 0x1c000000 0x04000000; Unrelated to this series, but we should remove that line. It's unlikely to be remotely correct. > sdhci@c8000400 { > + status = "okay"; > cd-gpios = <&gpio 69 0>; /* gpio PI5 */ > wp-gpios = <&gpio 57 0>; /* gpio PH1 */ > power-gpios = <&gpio 70 0>; /* gpio PI6 */ > + bus-width = <4>; > }; In an earlier version of these patches, I think you'd made the cd-gpios flags be "3" not "0", and I'd pointed out that doesn't match the kernel's. It turns out that on most (if not all) boards, cd-gpios should actually be marked active-low, so the flags should likely be "1" (not 3; bit 1 isn't defined to mean anything). This is true for all the NVIDIA boards, and Paz00 and TrimSlice. Joseph Lo is waiting for confirmation from Thierry and Lucas on their boards before re-spinning the patch to update them too. See: http://www.spinics.net/lists/linux-mmc/msg19134.html http://www.spinics.net/lists/linux-mmc/msg19139.html > diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts > /memreserve/ 0x1c000000 0x04000000; Same here, except that value is definitely always incorrect; memory starts at 0x80000000 on Tegra30, so that range never matches memory.
Stephen, On Wed, Feb 20, 2013 at 3:35 PM, Stephen Warren <swarren@wwwdotorg.org> wrote: > On 02/20/2013 02:05 PM, Tom Warren wrote: >> Linux dts files were used for those boards that didn't already >> have sdhci info populated. Tamonten has their own dtsi file with >> common sdhci nodes (sourced from Linux). > > So this patch now does a two unrelated things: > > a) Switches from /include/ to #include. > b) A bunch of changes for the SDHCI properties. > > Those should really be separate patches. I'll split 'em. > >> diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts > >> -/include/ ARCH_CPU_DTS >> +#include ARCH_CPU_DTS > > I think we should get rid of ARCH_CPU_DTS too. The only reason it ever > existed was because we were using dtc's include processing and had to > work around some issue with that (I can't remember exactly what, but > Simon will). Now that we're using cpp's include processing, we can > simply write: > > #include "tegra20.dtsi". That can be done later in a dts include file cleanup patch for all the DT builds/files. What is there now works fine. > >> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts > >> /memreserve/ 0x1c000000 0x04000000; > > Unrelated to this series, but we should remove that line. It's unlikely > to be remotely correct. Yep, saw those (tegra30, too), but didn't want to fix 'em here. I'll do it in a separate patch later. > >> sdhci@c8000400 { >> + status = "okay"; >> cd-gpios = <&gpio 69 0>; /* gpio PI5 */ >> wp-gpios = <&gpio 57 0>; /* gpio PH1 */ >> power-gpios = <&gpio 70 0>; /* gpio PI6 */ >> + bus-width = <4>; >> }; > > In an earlier version of these patches, I think you'd made the cd-gpios > flags be "3" not "0", and I'd pointed out that doesn't match the > kernel's. It turns out that on most (if not all) boards, cd-gpios should > actually be marked active-low, so the flags should likely be "1" (not 3; > bit 1 isn't defined to mean anything). This is true for all the NVIDIA > boards, and Paz00 and TrimSlice. Joseph Lo is waiting for confirmation > from Thierry and Lucas on their boards before re-spinning the patch to > update them too. Card-detect works fine (at least, on Seaboard). There never was an earlier version with cd-gpios flags with anything other than 0. It was power-gpios for Seaboard that had its flags set to 3 in a ChromeOS version of U-Boot that I originally copied the DT sdhci info from, and I've fixed that. > > See: > http://www.spinics.net/lists/linux-mmc/msg19134.html > http://www.spinics.net/lists/linux-mmc/msg19139.html > >> diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts > >> /memreserve/ 0x1c000000 0x04000000; > > Same here, except that value is definitely always incorrect; memory > starts at 0x80000000 on Tegra30, so that range never matches memory.
On 02/20/2013 04:01 PM, Tom Warren wrote: > Stephen, > > On Wed, Feb 20, 2013 at 3:35 PM, Stephen Warren <swarren@wwwdotorg.org> wrote: >> On 02/20/2013 02:05 PM, Tom Warren wrote: >>> Linux dts files were used for those boards that didn't already >>> have sdhci info populated. Tamonten has their own dtsi file with >>> common sdhci nodes (sourced from Linux). >> >> So this patch now does a two unrelated things: >> >> a) Switches from /include/ to #include. >> b) A bunch of changes for the SDHCI properties. >> >> Those should really be separate patches. > I'll split 'em. > >> >>> diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts >> >>> -/include/ ARCH_CPU_DTS >>> +#include ARCH_CPU_DTS >> >> I think we should get rid of ARCH_CPU_DTS too. The only reason it ever >> existed was because we were using dtc's include processing and had to >> work around some issue with that (I can't remember exactly what, but >> Simon will). Now that we're using cpp's include processing, we can >> simply write: >> >> #include "tegra20.dtsi". > That can be done later in a dts include file cleanup patch for all the > DT builds/files. What is there now works fine. Sigh. But if you're using cpp now, then removing the use of ARCH_CPU_DTS is logically part of that. I agree it works now, but it's far more important to get it right than just make it work. >>> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts >> >>> /memreserve/ 0x1c000000 0x04000000; >> >> Unrelated to this series, but we should remove that line. It's unlikely >> to be remotely correct. > Yep, saw those (tegra30, too), but didn't want to fix 'em here. I'll > do it in a separate patch later. > >> >>> sdhci@c8000400 { >>> + status = "okay"; >>> cd-gpios = <&gpio 69 0>; /* gpio PI5 */ >>> wp-gpios = <&gpio 57 0>; /* gpio PH1 */ >>> power-gpios = <&gpio 70 0>; /* gpio PI6 */ >>> + bus-width = <4>; >>> }; >> >> In an earlier version of these patches, I think you'd made the cd-gpios >> flags be "3" not "0", and I'd pointed out that doesn't match the >> kernel's. It turns out that on most (if not all) boards, cd-gpios should >> actually be marked active-low, so the flags should likely be "1" (not 3; >> bit 1 isn't defined to mean anything). This is true for all the NVIDIA >> boards, and Paz00 and TrimSlice. Joseph Lo is waiting for confirmation >> from Thierry and Lucas on their boards before re-spinning the patch to >> update them too. > > Card-detect works fine (at least, on Seaboard). That's likely because nothing in the code actually uses the GPIO flags field, but rather assumes that the GPIO is active low. We should still correct this error in the DT so that what the DT asserts is true actually is true. > There never was an > earlier version with cd-gpios flags with anything other than 0. It was > power-gpios for Seaboard that had its flags set to 3 in a ChromeOS > version of U-Boot that I originally copied the DT sdhci info from, and > I've fixed that. Ah, OK.
Stephen, On Wed, Feb 20, 2013 at 5:15 PM, Stephen Warren <swarren@wwwdotorg.org> wrote: > On 02/20/2013 04:01 PM, Tom Warren wrote: >> Stephen, >> >> On Wed, Feb 20, 2013 at 3:35 PM, Stephen Warren <swarren@wwwdotorg.org> wrote: >>> On 02/20/2013 02:05 PM, Tom Warren wrote: >>>> Linux dts files were used for those boards that didn't already >>>> have sdhci info populated. Tamonten has their own dtsi file with >>>> common sdhci nodes (sourced from Linux). >>> >>> So this patch now does a two unrelated things: >>> >>> a) Switches from /include/ to #include. >>> b) A bunch of changes for the SDHCI properties. >>> >>> Those should really be separate patches. >> I'll split 'em. >> >>> >>>> diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts >>> >>>> -/include/ ARCH_CPU_DTS >>>> +#include ARCH_CPU_DTS >>> >>> I think we should get rid of ARCH_CPU_DTS too. The only reason it ever >>> existed was because we were using dtc's include processing and had to >>> work around some issue with that (I can't remember exactly what, but >>> Simon will). Now that we're using cpp's include processing, we can >>> simply write: >>> >>> #include "tegra20.dtsi". >> That can be done later in a dts include file cleanup patch for all the >> DT builds/files. What is there now works fine. > > Sigh. But if you're using cpp now, then removing the use of ARCH_CPU_DTS > is logically part of that. > > I agree it works now, but it's far more important to get it right than > just make it work. Since I have to touch the dts files yet again to put the cd-gpios flag change in, I'll change all the ARCH_CPU_DTS occurrences to "tegra20.dtsi". Sigh. ;) > >>>> diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts >>> >>>> /memreserve/ 0x1c000000 0x04000000; >>> >>> Unrelated to this series, but we should remove that line. It's unlikely >>> to be remotely correct. >> Yep, saw those (tegra30, too), but didn't want to fix 'em here. I'll >> do it in a separate patch later. >> >>> >>>> sdhci@c8000400 { >>>> + status = "okay"; >>>> cd-gpios = <&gpio 69 0>; /* gpio PI5 */ >>>> wp-gpios = <&gpio 57 0>; /* gpio PH1 */ >>>> power-gpios = <&gpio 70 0>; /* gpio PI6 */ >>>> + bus-width = <4>; >>>> }; >>> >>> In an earlier version of these patches, I think you'd made the cd-gpios >>> flags be "3" not "0", and I'd pointed out that doesn't match the >>> kernel's. It turns out that on most (if not all) boards, cd-gpios should >>> actually be marked active-low, so the flags should likely be "1" (not 3; >>> bit 1 isn't defined to mean anything). This is true for all the NVIDIA >>> boards, and Paz00 and TrimSlice. Joseph Lo is waiting for confirmation >>> from Thierry and Lucas on their boards before re-spinning the patch to >>> update them too. >> >> Card-detect works fine (at least, on Seaboard). > > That's likely because nothing in the code actually uses the GPIO flags > field, but rather assumes that the GPIO is active low. > > We should still correct this error in the DT so that what the DT asserts > is true actually is true. > >> There never was an >> earlier version with cd-gpios flags with anything other than 0. It was >> power-gpios for Seaboard that had its flags set to 3 in a ChromeOS >> version of U-Boot that I originally copied the DT sdhci info from, and >> I've fixed that. > > Ah, OK.
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index d06cd12..ee08962 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -1,4 +1,4 @@ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "nvidia,tegra114"; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 9a89685..3805750 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -1,4 +1,4 @@ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "nvidia,tegra20"; @@ -318,24 +318,32 @@ sdhci@c8000000 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000000 0x200>; - interrupts = < 46 >; + interrupts = <0 14 0x04>; + clocks = <&tegra_car 14>; + status = "disabled"; }; sdhci@c8000200 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000200 0x200>; - interrupts = < 47 >; + interrupts = <0 15 0x04>; + clocks = <&tegra_car 9>; + status = "disabled"; }; sdhci@c8000400 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000400 0x200>; - interrupts = < 51 >; + interrupts = <0 19 0x04>; + clocks = <&tegra_car 69>; + status = "disabled"; }; sdhci@c8000600 { compatible = "nvidia,tegra20-sdhci"; reg = <0xc8000600 0x200>; - interrupts = < 63 >; + interrupts = <0 31 0x04>; + clocks = <&tegra_car 15>; + status = "disabled"; }; }; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 7b8126f..561c617 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -1,4 +1,4 @@ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" / { compatible = "nvidia,tegra30"; diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts index e46afbe..a9a07f9 100644 --- a/board/avionic-design/dts/tegra20-medcom-wide.dts +++ b/board/avionic-design/dts/tegra20-medcom-wide.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Medcom-Wide"; @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts index 3e6cce0..20016f2 100644 --- a/board/avionic-design/dts/tegra20-plutux.dts +++ b/board/avionic-design/dts/tegra20-plutux.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Plutux"; @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index bf3ff1d..1d7cf89 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include "tegra20-tamonten.dtsi" / { model = "Avionic Design Tamonten Evaluation Carrier"; @@ -8,6 +8,7 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; }; memory { diff --git a/board/compal/dts/tegra20-paz00.dts b/board/compal/dts/tegra20-paz00.dts index 31b064d..6041f29 100644 --- a/board/compal/dts/tegra20-paz00.dts +++ b/board/compal/dts/tegra20-paz00.dts @@ -1,13 +1,15 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { - model = "Toshiba AC100 / Dynabook AZ"; - compatible = "compal,paz00", "nvidia,tegra20"; + model = "Toshiba AC100 / Dynabook AZ"; + compatible = "compal,paz00", "nvidia,tegra20"; aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000000"; }; memory { @@ -53,6 +55,19 @@ status = "disabled"; }; + sdhci@c8000000 { + status = "okay"; + cd-gpios = <&gpio 173 0>; /* gpio PV5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 169 0>; /* gpio PV1 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; + lcd_panel: panel { /* PAZ00 has 1024x600 */ clock = <54030000>; diff --git a/board/compulab/dts/tegra20-trimslice.dts b/board/compulab/dts/tegra20-trimslice.dts index 7aeed67..929e12e 100644 --- a/board/compulab/dts/tegra20-trimslice.dts +++ b/board/compulab/dts/tegra20-trimslice.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "Compulab TrimSlice board"; @@ -9,6 +9,8 @@ aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000000"; }; memory { @@ -47,4 +49,16 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000000 { + status = "okay"; + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 121 0>; /* gpio PP1 */ + wp-gpios = <&gpio 122 0>; /* gpio PP2 */ + bus-width = <4>; + }; }; diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index 7315577..a3e7863 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "NVIDIA Dalmore"; diff --git a/board/nvidia/dts/tegra20-harmony.dts b/board/nvidia/dts/tegra20-harmony.dts index aeda3a1..d2952f8 100644 --- a/board/nvidia/dts/tegra20-harmony.dts +++ b/board/nvidia/dts/tegra20-harmony.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "NVIDIA Tegra20 Harmony evaluation board"; @@ -9,6 +9,8 @@ aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000200"; }; memory { @@ -52,4 +54,20 @@ usb@c5004000 { nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ }; + + sdhci@c8000200 { + status = "okay"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra20-seaboard.dts b/board/nvidia/dts/tegra20-seaboard.dts index 527a296..9e96761 100644 --- a/board/nvidia/dts/tegra20-seaboard.dts +++ b/board/nvidia/dts/tegra20-seaboard.dts @@ -1,7 +1,7 @@ /dts-v1/; /memreserve/ 0x1c000000 0x04000000; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "NVIDIA Seaboard"; @@ -12,14 +12,15 @@ }; aliases { - /* This defines the order of our USB ports */ + /* This defines the order of our ports */ usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; - i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -156,13 +157,16 @@ }; sdhci@c8000400 { + status = "okay"; cd-gpios = <&gpio 69 0>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <4>; }; sdhci@c8000600 { - support-8bit; + status = "okay"; + bus-width = <8>; }; lcd_panel: panel { diff --git a/board/nvidia/dts/tegra20-ventana.dts b/board/nvidia/dts/tegra20-ventana.dts index 3e5e39d..86dfcc7 100644 --- a/board/nvidia/dts/tegra20-ventana.dts +++ b/board/nvidia/dts/tegra20-ventana.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "NVIDIA Tegra20 Ventana evaluation board"; @@ -8,6 +8,8 @@ aliases { usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -41,4 +43,17 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000400 { + status = "okay"; + cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + wp-gpios = <&gpio 57 0>; /* gpio PH1 */ + power-gpios = <&gpio 70 0>; /* gpio PI6 */ + bus-width = <4>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra20-whistler.dts b/board/nvidia/dts/tegra20-whistler.dts index 4579557..47063f1 100644 --- a/board/nvidia/dts/tegra20-whistler.dts +++ b/board/nvidia/dts/tegra20-whistler.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "NVIDIA Tegra20 Whistler evaluation board"; @@ -9,6 +9,8 @@ aliases { i2c0 = "/i2c@7000d000"; usb0 = "/usb@c5008000"; + sdhci0 = "/sdhci@c8000600"; + sdhci1 = "/sdhci@c8000400"; }; memory { @@ -57,4 +59,15 @@ usb@c5004000 { status = "disabled"; }; + + sdhci@c8000400 { + status = "okay"; + wp-gpios = <&gpio 173 0>; /* gpio PV5 */ + bus-width = <8>; + }; + + sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + }; }; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts index f9f80c5..f7ea07a 100644 --- a/board/nvidia/dts/tegra30-cardhu.dts +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -1,7 +1,7 @@ /dts-v1/; /memreserve/ 0x1c000000 0x04000000; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "NVIDIA Cardhu"; diff --git a/board/toradex/dts/tegra20-colibri_t20_iris.dts b/board/toradex/dts/tegra20-colibri_t20_iris.dts index c29b43a..4e915c7 100644 --- a/board/toradex/dts/tegra20-colibri_t20_iris.dts +++ b/board/toradex/dts/tegra20-colibri_t20_iris.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ ARCH_CPU_DTS +#include ARCH_CPU_DTS / { model = "Toradex Colibri T20"; @@ -10,6 +10,7 @@ usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; usb2 = "/usb@c5004000"; + sdhci0 = "/sdhci@c8000600"; }; usb@c5000000 { @@ -35,4 +36,10 @@ compatible = "nand-flash"; }; }; + + sdhci@c8000600 { + status = "okay"; + cd-gpios = <&gpio 23 0>; /* gpio PC7 */ + bus-width = <4>; + }; };