diff mbox series

[1/4] pinctrl: amd: fix incorrect way to disable debounce filter

Message ID 20201104160344.4929-2-coiby.xu@gmail.com
State New
Headers show
Series [1/4] pinctrl: amd: fix incorrect way to disable debounce filter | expand

Commit Message

Coiby Xu Nov. 4, 2020, 4:03 p.m. UTC 
The correct way to disable debounce filter is to clear bit 5 and 6
of the register.

Cc: Hans de Goede <hdegoede@redhat.com>
Message-ID: <df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com>
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
---
 drivers/pinctrl/pinctrl-amd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--
2.28.0

Comments

Andy Shevchenko Nov. 4, 2020, 8:38 p.m. UTC | #1 
On Wed, Nov 4, 2020 at 6:05 PM Coiby Xu <coiby.xu@gmail.com> wrote:
>
> The correct way to disable debounce filter is to clear bit 5 and 6
> of the register.
>
> Cc: Hans de Goede <hdegoede@redhat.com>

> Message-ID: <df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com>

Can you use a Link tag with proper lore.kernel.org URL?
Coiby Xu Nov. 4, 2020, 11:08 p.m. UTC | #2 
On Wed, Nov 04, 2020 at 10:38:32PM +0200, Andy Shevchenko wrote:
>On Wed, Nov 4, 2020 at 6:05 PM Coiby Xu <coiby.xu@gmail.com> wrote:
>>
>> The correct way to disable debounce filter is to clear bit 5 and 6
>> of the register.
>>
>> Cc: Hans de Goede <hdegoede@redhat.com>
>
>> Message-ID: <df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com>
>
>Can you use a Link tag with proper lore.kernel.org URL?
>
Thank you for the suggestion. Applied in v2.

>--
>With Best Regards,
>Andy Shevchenko

--
Best regards,
Coiby
diff mbox series

Patch

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 9a760f5cd7ed..d6b2b4bd337c 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -166,14 +166,14 @@  static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
 		} else {
-			pin_reg &= ~DB_CNTRl_MASK;
+			pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 			ret = -EINVAL;
 		}
 	} else {
 		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
 		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
 		pin_reg &= ~DB_TMR_OUT_MASK;
-		pin_reg &= ~DB_CNTRl_MASK;
+		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
 	}
 	writel(pin_reg, gpio_dev->base + offset * 4);
 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);