diff mbox series

[2/2] powerpc: Document issues with TM on POWER9

Message ID 20180622061452.19016-2-mikey@neuling.org (mailing list archive)
State Superseded
Headers show
Series [1/2] powerpc: Document issues with the DAWR on POWER9 | expand

Commit Message

Michael Neuling June 22, 2018, 6:14 a.m. UTC 
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
 .../powerpc/transactional_memory.txt          | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

Comments

Stewart Smith June 22, 2018, 7:01 a.m. UTC | #1 
Michael Neuling <mikey@neuling.org> writes:
> +POWER9C DD1.2 and above are only avaliable with POWERNV and hence

PowerVM, not POWERNV
Segher Boessenkool June 22, 2018, 5:27 p.m. UTC | #2 
On Fri, Jun 22, 2018 at 04:14:52PM +1000, Michael Neuling wrote:
> +degredation. Host userspace has TM disabled

"degradation"

> +POWER9C DD1.2 and above are only avaliable with POWERNV and hence

"available"


Segher
diff mbox series

Patch

diff --git a/Documentation/powerpc/transactional_memory.txt b/Documentation/powerpc/transactional_memory.txt
index e32fdbb4c9..b254eab517 100644
--- a/Documentation/powerpc/transactional_memory.txt
+++ b/Documentation/powerpc/transactional_memory.txt
@@ -198,3 +198,47 @@  presented).  The transaction cannot then be continued and will take the failure
 handler route.  Furthermore, the transactional 2nd register state will be
 inaccessible.  GDB can currently be used on programs using TM, but not sensibly
 in parts within transactions.
+
+POWER9
+======
+
+TM on POWER9 has issues with storing the complete register state. This
+is described in this commit:
+
+    commit 4bb3c7a0208fc13ca70598efd109901a7cd45ae7
+    Author: Paul Mackerras <paulus@ozlabs.org>
+    Date:   Wed Mar 21 21:32:01 2018 +1100
+    KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9
+
+To account for this different POWER9 chips have TM enabled in
+different ways.
+
+On POWER9N DD2.01 and below, TM is disabled. ie
+HWCAP2[PPC_FEATURE2_HTM] is not set.
+
+On POWER9N DD2.1 TM is configured by firmware to always abort a
+transaction when tm suspend occurs. So tsuspend will cause a
+transaction to be aborted and rolled back. Kernel exceptions will also
+cause the transaction to be aborted and rolled back and the exception
+will not occur. If userspace constructs a sigcontext that enables TM
+suspend, the sigcontext will be rejected by the kernel. This mode is
+advertised to users with HWCAP2[PPC_FEATURE2_HTM_NO_SUSPEND] set.
+HWCAP2[PPC_FEATURE2_HTM] is not set in this mode.
+
+On POWER9N DD2.2 and above, KVM and POWERVM emulate TM for guests (as
+descibed in commit 4bb3c7a0208f), hence TM is enabled for guests
+ie. HWCAP2[PPC_FEATURE2_HTM] is set for guest userspace. Guests that
+makes heavy use of TM suspend (tsuspend or kernel suspend) will result
+in traps into the hypervisor and hence will suffer a performance
+degredation. Host userspace has TM disabled
+ie. HWCAP2[PPC_FEATURE2_HTM] is not set. (although we make enable it
+at some point in the future if we bring the emulation into host
+userspace context switching).
+
+POWER9C DD1.2 and above are only avaliable with POWERNV and hence
+Linux only runs as a guest. On these systems TM is emulated like on
+POWER9N DD2.2.
+
+Guest migration from POWER8 to POWER9 will work with POWER9N DD2.2 and
+POWER9C DD1.2. Since earlier POWER9 processors don't support TM
+emulation, migration from POWER8 to POWER9 is not supported there.