| Message ID | 20180503225537.20748-6-digetx@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Restore ULPI USB on Tegra20 | expand |
On Fri, May 04, 2018 at 01:55:37AM +0300, Dmitry Osipenko wrote: > Commit 4c9a27a6c66d ("ARM: tegra: Fix ULPI regression on Tegra20") changed > "ulpi-link" clock from CDEV2 to PLL_P_OUT4. Turned out that PLL_P_OUT4 is > the parent of CDEV2 clock and original clock setup of "ulpi-link" was > correct. The reverted patch was fixing USB for one board and broke the > other, now Tegra's clk driver correctly sets parent for the CDEV2 clock > and hence patch could be reverted safely, restoring USB for all of the > boards. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> > Tested-by: Marcel Ziswiler <marcel@ziswiler.com> > Tested-by: Marc Dietrich <marvin24@gmx.de> > --- > arch/arm/boot/dts/tegra20.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Is it still true that this patch alone fixes the known regression? I'm just asking because the remainder of the series, even though it sounds to be the right thing to do, is fairly big for a fix against v4.17. So if this alone fixes the regression I think it'd be best to queue it up for v4.17 and get the rest of the patches into v4.18. Thierry
On 04.05.2018 13:40, Thierry Reding wrote: > On Fri, May 04, 2018 at 01:55:37AM +0300, Dmitry Osipenko wrote: >> Commit 4c9a27a6c66d ("ARM: tegra: Fix ULPI regression on Tegra20") changed >> "ulpi-link" clock from CDEV2 to PLL_P_OUT4. Turned out that PLL_P_OUT4 is >> the parent of CDEV2 clock and original clock setup of "ulpi-link" was >> correct. The reverted patch was fixing USB for one board and broke the >> other, now Tegra's clk driver correctly sets parent for the CDEV2 clock >> and hence patch could be reverted safely, restoring USB for all of the >> boards. >> >> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> >> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> >> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> >> Tested-by: Marc Dietrich <marvin24@gmx.de> >> --- >> arch/arm/boot/dts/tegra20.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) > > Is it still true that this patch alone fixes the known regression? I'm > just asking because the remainder of the series, even though it sounds > to be the right thing to do, is fairly big for a fix against v4.17. Yes, Marcel says that reverting just this patch works for him now. > So if this alone fixes the regression I think it'd be best to queue it > up for v4.17 and get the rest of the patches into v4.18. Sounds good. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 0a7136462a1a..983dd5c14794 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -741,7 +741,7 @@ phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT4>; + <&tegra_car TEGRA20_CLK_CDEV2>; clock-names = "reg", "pll_u", "ulpi-link"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads";
Commit 4c9a27a6c66d ("ARM: tegra: Fix ULPI regression on Tegra20") changed "ulpi-link" clock from CDEV2 to PLL_P_OUT4. Turned out that PLL_P_OUT4 is the parent of CDEV2 clock and original clock setup of "ulpi-link" was correct. The reverted patch was fixing USB for one board and broke the other, now Tegra's clk driver correctly sets parent for the CDEV2 clock and hence patch could be reverted safely, restoring USB for all of the boards. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Marc Dietrich <marvin24@gmx.de> --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)