From patchwork Thu May 3 22:55:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 908344 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="VtA0GXQ8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40cVrr4PdWz9s2t for ; Fri, 4 May 2018 08:57:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751403AbeECW4T (ORCPT ); Thu, 3 May 2018 18:56:19 -0400 Received: from mail-lf0-f65.google.com ([209.85.215.65]:39663 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751116AbeECW4R (ORCPT ); Thu, 3 May 2018 18:56:17 -0400 Received: by mail-lf0-f65.google.com with SMTP id j193-v6so28317102lfg.6; Thu, 03 May 2018 15:56:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Hen+wjG6wbWxgtH2nfl8nVcZ7pTN6V8XvKMD6k7Sj8U=; b=VtA0GXQ8eS+JnOqVRjjTa4spQZqRcCNP5TzR8WJNEqFBJSAXT1FE71hrUMsDWAszGY lU4J5GktJM5Wag5dePBgw5AtfiFPnaU+HuaV1AzmX3rm3HUVVgNJ7EQltZ7SIryTVjLg vRIa4JMIW2DJ3dr6amxukg/0WyRyP19NQD/eX16xrGCU0D/NKzQlIIhhJyu4yJtFR9eC zWQv4oZtih96yxijz6BZDxqVDOo94eHNyj7qaClLXXRAqa9tZl23TKlSLReF25LatoYg CoaS8nO1JtPedSThPieSbqyBvyXGRCXreWd2LchwuMaiikhxqlPxw2RBrcbNa36SFEeN pIvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hen+wjG6wbWxgtH2nfl8nVcZ7pTN6V8XvKMD6k7Sj8U=; b=Ohybd4UafnMntlFmzje13IqBlrhZ2B9efoYGSYarnxckyYn2KTwrEKMjW2BvuRkHcq p/C8iiFRDNNd4LPlewUfAIfzGEbeYUcLigCkNXQ3IeIKUqObEdcs6B3Ps7+ya9zGwEUH sLHOiHijsDmxoNnj8kteJyHj6WQL1ONA2gdzIplyrzonMIVRACTd9sG564rFW5M748a7 nL+IybOuu+Luv0BRlEyMV5yIBvUBfgHb9fu0J0jxnUqNJ+0Fw17yIhUjz2WoY5tiYx0R +fsz1K/snzYBbwe75SBY5z9EN/DtP1TIqgkz9V62OLz79mP3RHU8u/MdsTKHan7QD6m/ QOHw== X-Gm-Message-State: ALQs6tCSxwXux8Axy2LObWx20AFZDbQMbG2Fj7ZcFRDVxDS9XwJpff7f j9UrjFOcd2lj+zYrzY1iF5k= X-Google-Smtp-Source: AB8JxZqv9S53B8TaRaNFom+EeRh+bO2NG7z30nC1ME20eFCxwQtiqZcTxQj+zBFeDf8cu1G5I2wajQ== X-Received: by 2002:a19:1428:: with SMTP id k40-v6mr15035904lfi.19.1525388175489; Thu, 03 May 2018 15:56:15 -0700 (PDT) Received: from localhost.localdomain (ppp109-252-91-130.pppoe.spdop.ru. [109.252.91.130]) by smtp.gmail.com with ESMTPSA id h20-v6sm2995858ljj.85.2018.05.03.15.56.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 May 2018 15:56:14 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers Date: Fri, 4 May 2018 01:55:33 +0300 Message-Id: <20180503225537.20748-2-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503225537.20748-1-digetx@gmail.com> References: <20180503225537.20748-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as a parent. Add these dividers in order to be able to provide that parent option. Signed-off-by: Dmitry Osipenko Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Tested-by: Marc Dietrich Acked-by: Peter De Schrijver Acked-by: Stephen Boyd --- drivers/clk/tegra/clk-tegra20.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 0ee56dd04cec..ad5a7b5e3a39 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -26,6 +26,8 @@ #include "clk.h" #include "clk-id.h" +#define MISC_CLK_ENB 0x48 + #define OSC_CTRL 0x50 #define OSC_CTRL_OSC_FREQ_MASK (3<<30) #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) @@ -831,6 +833,18 @@ static void __init tegra20_periph_clk_init(void) periph_clk_enb_refcnt); clks[TEGRA20_CLK_PEX] = clk; + /* dev1 OSC divider */ + clk_register_divider(NULL, "dev1_osc_div", "clk_m", + 0, clk_base + MISC_CLK_ENB, 22, 2, + CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, + NULL); + + /* dev2 OSC divider */ + clk_register_divider(NULL, "dev2_osc_div", "clk_m", + 0, clk_base + MISC_CLK_ENB, 20, 2, + CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY, + NULL); + /* cdev1 */ clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000); clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, From patchwork Thu May 3 22:55:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 908346 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="r18UfBGh"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40cVs43j6wz9s2t for ; Fri, 4 May 2018 08:57:12 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751533AbeECW5C (ORCPT ); Thu, 3 May 2018 18:57:02 -0400 Received: from mail-lf0-f66.google.com ([209.85.215.66]:37689 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751339AbeECW4T (ORCPT ); Thu, 3 May 2018 18:56:19 -0400 Received: by mail-lf0-f66.google.com with SMTP id b23-v6so28311209lfg.4; Thu, 03 May 2018 15:56:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bjyf9Bn+HltNhb4OMyxy9n39mEczyfsL4RL2EwKlXMM=; b=r18UfBGhc9ZNxLLoeCvCrRHVyYK8kdY9M4upRR4ioDmyBaIlmNRX53RnJ5vlxpJEKn nLUSoIZKW+gl7EvTNhY+S7EJsJa4LSULDKKCpx5x6o4fTzqmRN2TAGgv+RMMG1HX/ajn t6PlB9hKU2anWlCmrZhaLDx/p/STYsxdactYcTmKSP9WgaA5odHrzCUfroiJwtOeNyl7 0zSx7GXO0adXgBRhyJje+AHCzlQLGuB9cm+fpNo6NeFUqAFsS/ylogyiOCgpLwFhBbRf ejKaRorQ75GjOeD6Qt75dvqVEdHQZqA5Ek+caGVEu8zOvud+qzZp0/oMGzdIznP5WKF4 rLog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bjyf9Bn+HltNhb4OMyxy9n39mEczyfsL4RL2EwKlXMM=; b=YxbhPOu/LuAd05ZyI/el+3icjKvGESLQgWQnsnlH/fq6hx8ekcV/lyIE1mj1s81yV4 HWu/YRO19tzCOl//YXP0CBfhLtzlykMiWqgabPkTisnTIPwEZkEhqG9YNUC4gFbDAH6J qxsp6b0wZqij3c1wLZ3Av1uX9Evz10JqV+vvn0zisfgPbgIyM9BULz4dkV4tf7/XTwaz wtp076QxqQVVwr0qjSKF7t2Yk+2rShA1dI7hFzWJsc+5XSZPWWNSmf0LpxKcmSjEWaIL 8tujf4NTxDjvaKEv/fpaQSjuNqt1lCojADSRrWOe3YbyrnsNosw5nnN4d9LAfIs3M7qx aIMQ== X-Gm-Message-State: ALQs6tBdPB4ambd5m227pXztvsZZox8jVoZPX0WRCfknHp2w8khJcaOf iY/CRV6g6tjhOXwH05dtUwY= X-Google-Smtp-Source: AB8JxZoFU5Vqvns0O/w54oSAbORkc0QndXDtPlWG+e3dya2ZGq+kFL5bt3JWyq2QQVTfRKuqtrbM5Q== X-Received: by 2002:a19:8e8e:: with SMTP id a14-v6mr16273908lfl.145.1525388177892; Thu, 03 May 2018 15:56:17 -0700 (PDT) Received: from localhost.localdomain (ppp109-252-91-130.pppoe.spdop.ru. [109.252.91.130]) by smtp.gmail.com with ESMTPSA id h20-v6sm2995858ljj.85.2018.05.03.15.56.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 May 2018 15:56:17 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] clk: tegra20: Correct parents of CDEV1/2 clocks Date: Fri, 4 May 2018 01:55:35 +0300 Message-Id: <20180503225537.20748-4-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503225537.20748-1-digetx@gmail.com> References: <20180503225537.20748-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Parents of CDEV1/2 clocks are determined by muxing of the corresponding pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the corresponding muxes to fix the parents. Signed-off-by: Dmitry Osipenko Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Tested-by: Marc Dietrich Acked-by: Peter De Schrijver Acked-by: Stephen Boyd --- drivers/clk/tegra/clk-tegra20.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index ad5a7b5e3a39..636500a98561 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -846,14 +846,12 @@ static void __init tegra20_periph_clk_init(void) NULL); /* cdev1 */ - clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, 0, 26000000); - clk = tegra_clk_register_periph_gate("cdev1", "cdev1_fixed", 0, + clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0, clk_base, 0, 94, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV1] = clk; /* cdev2 */ - clk = clk_register_fixed_rate(NULL, "cdev2_fixed", NULL, 0, 26000000); - clk = tegra_clk_register_periph_gate("cdev2", "cdev2_fixed", 0, + clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0, clk_base, 0, 93, periph_clk_enb_refcnt); clks[TEGRA20_CLK_CDEV2] = clk; From patchwork Thu May 3 22:55:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 908343 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="iNxWDVEr"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40cVrn4Wqhz9s2t for ; Fri, 4 May 2018 08:56:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751262AbeECW4n (ORCPT ); Thu, 3 May 2018 18:56:43 -0400 Received: from mail-lf0-f67.google.com ([209.85.215.67]:41363 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751404AbeECW4U (ORCPT ); Thu, 3 May 2018 18:56:20 -0400 Received: by mail-lf0-f67.google.com with SMTP id o123-v6so28299493lfe.8; Thu, 03 May 2018 15:56:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Evje7YaK8dK+toihbPtICR2AoZDZE//cJAHLsBBaCmU=; b=iNxWDVErplRELWVtRhJJ3CyWk3eTlcWr62vlW6zIMLjKv7at8sDQR3Lp0UzLsRR72P ud4p50UbeWCQKVlKLsNhSSSlOSqGfMl9aAdDT+2vLRbYFFKApa16CHRAGTDN327o8Mjg b3W92308hCaKRm6sMjItx+q6VtkUYtQ1zGPyPdo4edRu2ZTMk8QriAIIdHQCEPegeWhG 3DQETqdYnexVKwDNnQeKy7Kt6bPtLE+eMddoenbLfCQSQvAeXoE21HvbuTFEkRTiSYnu LO4OLwovMu5wukCzfFa8xjQadDgwaqz2MbxgwwCDaAshjWpq+zJHjiDrwVHK4L0rBRQP BU6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Evje7YaK8dK+toihbPtICR2AoZDZE//cJAHLsBBaCmU=; b=FgNioMm8QrihHEp66125a6fag/GOvaD3Y+8qGarJbLOZgRfVc3rkdMMnwlfZuPz/fG 8LYzXV7WU5oif0oHV34j5l2txVawvrFQJnBgox61/gHAnOmfX1JZmW//eUxj4Bbdjjlm x459NLjYoAmkJcN/1YJNm1We/bPYxg58Qb6XhmjoD7oZYTcJmI1WYunDU41zStegu2/l 5p3oWkiZmaJrbzvya1Xr/pTw90yDpLlE5TotVT1SbdwOBKbWMnafklKOmd/WXmSzBmyJ otti3wW8CjCXxFfqbu4gxSKLgPGR0GbgODxjEEC6BArn8nS7ubLTfGmX2EksdhZJbJ/h PqLQ== X-Gm-Message-State: ALQs6tBXZVGKTZHaB5XjrDvXQ96TyImxp3LbcQ5ruYlQob5f7JvOfju9 BGcvajUFRVZSJCsMkF/P7P0= X-Google-Smtp-Source: AB8JxZrcFeh3We+yeiPo3Ko7AzCSpaRTSM/3aN75AOXSF1pVFrT1gKAo1C8b7wutA/SSF1qetswAxw== X-Received: by 2002:a19:d853:: with SMTP id p80-v6mr2727198lfg.36.1525388178974; Thu, 03 May 2018 15:56:18 -0700 (PDT) Received: from localhost.localdomain (ppp109-252-91-130.pppoe.spdop.ru. [109.252.91.130]) by smtp.gmail.com with ESMTPSA id h20-v6sm2995858ljj.85.2018.05.03.15.56.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 May 2018 15:56:18 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/4] clk: tegra: Add quirk for getting CDEV1/2 clocks Date: Fri, 4 May 2018 01:55:36 +0300 Message-Id: <20180503225537.20748-5-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503225537.20748-1-digetx@gmail.com> References: <20180503225537.20748-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org CDEV1 and CDEV2 clocks are a bit special case, their parent clock is created by the pinctrl driver. It should be possible for clk user to request these clocks before pinctrl driver got probed and hence user will get an orphaned clock. That might be undesirable because user expects parent clock to be enabled by the child, so let's return EPROBE_DEFER until parent clock appear. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index ba923f0d5953..04cbe7e9eff3 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -298,6 +298,38 @@ static struct reset_controller_dev rst_ctlr = { .of_reset_n_cells = 1, }; +static struct clk *tegra_of_clk_src_onecell_get(struct of_phandle_args *clkspec, + void *data) +{ + struct clk_hw *parent_hw; + struct clk_hw *hw; + struct clk *clk; + const char *name; + + clk = of_clk_src_onecell_get(clkspec, data); + if (IS_ERR(clk)) + return clk; + + name = __clk_get_name(clk); + + /* + * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent + * clock is created by the pinctrl driver. It is possible for clk user + * to request these clocks before pinctrl driver got probed and hence + * user will get an orphaned clock. That might be undesirable because + * user may expect parent clock to be enabled by the child. + */ + if (!strcmp(name, "cdev1") || !strcmp(name, "cdev2")) { + hw = __clk_get_hw(clk); + + parent_hw = clk_hw_get_parent(hw); + if (!parent_hw) + return ERR_PTR(-EPROBE_DEFER); + } + + return clk; +} + void __init tegra_add_of_provider(struct device_node *np) { int i; @@ -314,7 +346,7 @@ void __init tegra_add_of_provider(struct device_node *np) clk_data.clks = clks; clk_data.clk_num = clk_num; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + of_clk_add_provider(np, tegra_of_clk_src_onecell_get, &clk_data); rst_ctlr.of_node = np; rst_ctlr.nr_resets = periph_banks * 32 + num_special_reset; From patchwork Thu May 3 22:55:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 908341 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="XQ8h3VSs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40cVrS3Q6jz9s4r for ; Fri, 4 May 2018 08:56:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751116AbeECW4Y (ORCPT ); Thu, 3 May 2018 18:56:24 -0400 Received: from mail-lf0-f67.google.com ([209.85.215.67]:44043 "EHLO mail-lf0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751443AbeECW4W (ORCPT ); Thu, 3 May 2018 18:56:22 -0400 Received: by mail-lf0-f67.google.com with SMTP id h197-v6so28280206lfg.11; Thu, 03 May 2018 15:56:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AryoI7qCSgXn6g5HC62yneTVcnwLB99jJTxRS/k1/RU=; b=XQ8h3VSsvu/kf8EL03uRzJm95rWqWxTYspALZGF7Hp2jojR9D1Rf+kYYj974Lp4TlE h4WygJEmyAxLdp4kfWZda/PA/mnYxFx3WhK8ACw+FbqxED+ycrorgOER9qI1l9dJbhw3 i2bji9GgSP2FW2KXAX44Z2UFdbU4qMlaicRHkH9UJpGrSa1Jnpa7NMsOehDir4G4Cq6C XEwgYH3K6UYKOPXubfJ6MkcaC+k9gEmj4HVFir83SxkgoWabl8tmNrDsK95QmsuLwl+K QvBLHbjcJkrnllbTxDYNAFF7647cTb4OHFitlACxEOk3wKsc+pqqSCY+M+SqtQ6VHM2u 5ZkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AryoI7qCSgXn6g5HC62yneTVcnwLB99jJTxRS/k1/RU=; b=QbJceyVW8AFQoABPBbSIQR+yTlza1ThkOjvvI/ounm2q8fkIY3kD47M+2FnHuVxzVF hR1pbvzRLUC4tVNZIwtu+ph2AyFaSuEtndjUnbFUmN8rW1hfxQv4yl8bSkfjj0xPhDuU iLUVR3Cal21Tya8+WK3tBwMmkelAgynW92GIXNPJwmtPQ1nLSlNGQy4lBjfQaIt5n7xb 4cZzYxygp7BqisKLuApSjM3yasyiPf+U+RiYaZnL4RuHev7C665ytgBBTzgvmw0G9RUD TP6pnu7Jc5e5XOFUG+g03q2S6P7ACHlXmBKVWYhdqlqTR+dYfvlJQC40HwcTr+QO40Y+ pUOw== X-Gm-Message-State: ALQs6tDLtryjDRQiqR/afV+hWOJKh2hcU4v8ms+HdSsbs9fuV8BL0OzA ddKQh05lQiAb9JlQps4MJO8= X-Google-Smtp-Source: AB8JxZr43vHdK/rE961f4Qvkd6P/o6w7pOyDAVoNdHjKCp8P/P1nh8BjRnXxF1dMUrtov9G/zLnRTA== X-Received: by 2002:a2e:9797:: with SMTP id y23-v6mr18168834lji.52.1525388180084; Thu, 03 May 2018 15:56:20 -0700 (PDT) Received: from localhost.localdomain (ppp109-252-91-130.pppoe.spdop.ru. [109.252.91.130]) by smtp.gmail.com with ESMTPSA id h20-v6sm2995858ljj.85.2018.05.03.15.56.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 May 2018 15:56:19 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20" Date: Fri, 4 May 2018 01:55:37 +0300 Message-Id: <20180503225537.20748-6-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503225537.20748-1-digetx@gmail.com> References: <20180503225537.20748-1-digetx@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Commit 4c9a27a6c66d ("ARM: tegra: Fix ULPI regression on Tegra20") changed "ulpi-link" clock from CDEV2 to PLL_P_OUT4. Turned out that PLL_P_OUT4 is the parent of CDEV2 clock and original clock setup of "ulpi-link" was correct. The reverted patch was fixing USB for one board and broke the other, now Tegra's clk driver correctly sets parent for the CDEV2 clock and hence patch could be reverted safely, restoring USB for all of the boards. Signed-off-by: Dmitry Osipenko Reviewed-by: Marcel Ziswiler Tested-by: Marcel Ziswiler Tested-by: Marc Dietrich --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 0a7136462a1a..983dd5c14794 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -741,7 +741,7 @@ phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT4>; + <&tegra_car TEGRA20_CLK_CDEV2>; clock-names = "reg", "pll_u", "ulpi-link"; resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads";