| Message ID | 20170522062552.19026-3-wens@csie.org |
|---|---|
| State | New |
| Headers | show |
On Mon, May 22, 2017 at 02:25:48PM +0800, Chen-Yu Tsai wrote: > The divider of the audio PLL has an offset of 1. > Fix this in the driver. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Applied, thanks! Maxime
On Mon, May 22, 2017 at 3:20 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > On Mon, May 22, 2017 at 02:25:48PM +0800, Chen-Yu Tsai wrote: >> The divider of the audio PLL has an offset of 1. >> Fix this in the driver. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > Applied, thanks! So even with this patch applied, the audio is still slow and off pitch. It's even worse without this patch... Maybe it's time we added a special class of clks for the audio PLL to deal with sigma-delta modulation of the divider? ChenYu -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, May 22, 2017 at 03:35:57PM +0800, Chen-Yu Tsai wrote: > On Mon, May 22, 2017 at 3:20 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > On Mon, May 22, 2017 at 02:25:48PM +0800, Chen-Yu Tsai wrote: > >> The divider of the audio PLL has an offset of 1. > >> Fix this in the driver. > >> > >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > > > Applied, thanks! > > So even with this patch applied, the audio is still slow and off pitch. > It's even worse without this patch... > > Maybe it's time we added a special class of clks for the audio PLL > to deal with sigma-delta modulation of the divider? I'm not sure how feasible that would be and what it would look like, but you can give it a shot yes. Maxime
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index a9c5cc87d9d0..947f9f6e05d2 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -80,7 +80,7 @@ static struct ccu_nm pll_audio_clk = { .enable = BIT(31), .lock = BIT(2), .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), - .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0), + .m = _SUNXI_CCU_DIV(0, 6), .common = { .reg = SUN8I_A83T_PLL_AUDIO_REG, .lock_reg = CCU_SUN8I_A83T_LOCK_REG,
The divider of the audio PLL has an offset of 1. Fix this in the driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)