From patchwork Mon May 22 06:25:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 765261 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wWTFK6jMtz9s3s for ; Mon, 22 May 2017 16:26:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752019AbdEVG0I (ORCPT ); Mon, 22 May 2017 02:26:08 -0400 Received: from mirror2.csie.ntu.edu.tw ([140.112.30.76]:48708 "EHLO wens.csie.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751462AbdEVG0I (ORCPT ); Mon, 22 May 2017 02:26:08 -0400 Received: by wens.csie.org (Postfix, from userid 1000) id A39586008A; Mon, 22 May 2017 14:26:05 +0800 (CST) From: Chen-Yu Tsai To: Linus Walleij , Maxime Ripard Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 2/6] clk: sunxi-ng: a83t: Fix audio PLL divider offset Date: Mon, 22 May 2017 14:25:48 +0800 Message-Id: <20170522062552.19026-3-wens@csie.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170522062552.19026-1-wens@csie.org> References: <20170522062552.19026-1-wens@csie.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The divider of the audio PLL has an offset of 1. Fix this in the driver. Signed-off-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index a9c5cc87d9d0..947f9f6e05d2 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -80,7 +80,7 @@ static struct ccu_nm pll_audio_clk = { .enable = BIT(31), .lock = BIT(2), .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), - .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0), + .m = _SUNXI_CCU_DIV(0, 6), .common = { .reg = SUN8I_A83T_PLL_AUDIO_REG, .lock_reg = CCU_SUN8I_A83T_LOCK_REG,