diff mbox

[net-next] cxgb4: fix incorrect cim_la output for T6

Message ID 1495188738-20546-1-git-send-email-ganeshgr@chelsio.com
State Changes Requested, archived
Delegated to: David Miller
Headers show

Commit Message

Ganesh Goudar May 19, 2017, 10:12 a.m. UTC 
take care of UpDbgLaRdPtr[0-3] restriction for T6

Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
---
 drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

David Laight May 19, 2017, 2:17 p.m. UTC | #1 
From: Ganesh Goudar
> Sent: 19 May 2017 11:12
T6
> 
> take care of UpDbgLaRdPtr[0-3] restriction for T6
> 
> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
> ---
>  drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
> index aded42b96..917b46b 100644
> --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
> +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
> @@ -8268,6 +8268,13 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
>  		if (ret)
>  			break;
>  		idx = (idx + 1) & UPDBGLARDPTR_M;
> +
> +		/* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
> +		 * identify the 32-bit portion of the full 312-bit data
> +		 */
> +		if (is_t6(adap->params.chip))
> +			while ((idx & 0xf) > 9)
> +				idx = (idx + 1) % UPDBGLARDPTR_M;

Why the loop, maybe:
		if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
			idx = (idx & 0xf0) + 0x10;
		else
			idx++;
		idx &= UPDBGLARDPTR_M;

	David
Ganesh Goudar May 30, 2017, 11:53 a.m. UTC | #2 
On Friday, May 05/19/17, 2017 at 14:17:11 +0000, David Laight wrote:
> From: Ganesh Goudar
> > Sent: 19 May 2017 11:12
> T6
> > 
> > take care of UpDbgLaRdPtr[0-3] restriction for T6
> > 
> > Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com>
> > ---
> >  drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
> > index aded42b96..917b46b 100644
> > --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
> > +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
> > @@ -8268,6 +8268,13 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
> >  		if (ret)
> >  			break;
> >  		idx = (idx + 1) & UPDBGLARDPTR_M;
> > +
> > +		/* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
> > +		 * identify the 32-bit portion of the full 312-bit data
> > +		 */
> > +		if (is_t6(adap->params.chip))
> > +			while ((idx & 0xf) > 9)
> > +				idx = (idx + 1) % UPDBGLARDPTR_M;
> 
> Why the loop, maybe:
> 		if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
> 			idx = (idx & 0xf0) + 0x10;
> 		else
> 			idx++;
> 		idx &= UPDBGLARDPTR_M;
> 
> 	David
>
Yes, it is sensible I will send a v2, thanks David.

Thanks
diff mbox

Patch

diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index aded42b96..917b46b 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -8268,6 +8268,13 @@  int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
 		if (ret)
 			break;
 		idx = (idx + 1) & UPDBGLARDPTR_M;
+
+		/* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
+		 * identify the 32-bit portion of the full 312-bit data
+		 */
+		if (is_t6(adap->params.chip))
+			while ((idx & 0xf) > 9)
+				idx = (idx + 1) % UPDBGLARDPTR_M;
 	}
 restart:
 	if (cfg & UPDBGLAEN_F) {