From patchwork Fri May 19 10:12:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ganesh Goudar X-Patchwork-Id: 764560 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wTkQ928TGz9s0g for ; Fri, 19 May 2017 20:12:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754450AbdESKMr (ORCPT ); Fri, 19 May 2017 06:12:47 -0400 Received: from stargate.chelsio.com ([12.32.117.8]:6728 "EHLO stargate.chelsio.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751329AbdESKMq (ORCPT ); Fri, 19 May 2017 06:12:46 -0400 Received: from localhost (victim.blr.asicdesigners.com [10.193.185.129]) by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id v4JACfL6017523; Fri, 19 May 2017 03:12:43 -0700 From: Ganesh Goudar To: netdev@vger.kernel.org, davem@davemloft.net Cc: nirranjan@chelsio.com, indranil@chelsio.com, Ganesh Goudar Subject: [PATCH net-next] cxgb4: fix incorrect cim_la output for T6 Date: Fri, 19 May 2017 15:42:18 +0530 Message-Id: <1495188738-20546-1-git-send-email-ganeshgr@chelsio.com> X-Mailer: git-send-email 2.1.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org take care of UpDbgLaRdPtr[0-3] restriction for T6 Signed-off-by: Ganesh Goudar --- drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c index aded42b96..917b46b 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c @@ -8268,6 +8268,13 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) if (ret) break; idx = (idx + 1) & UPDBGLARDPTR_M; + + /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to + * identify the 32-bit portion of the full 312-bit data + */ + if (is_t6(adap->params.chip)) + while ((idx & 0xf) > 9) + idx = (idx + 1) % UPDBGLARDPTR_M; } restart: if (cfg & UPDBGLAEN_F) {