| Message ID | 1473924446-29927-1-git-send-email-clsee@altera.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > Adding new handoff for SDRAM ctrcfg.extratime1 which is > > required for stabil LPDDR2 operation > > ... stable ... > > Isn't SoCDK using DDR3 DRAM ? Yah, you are right where we won't need this patch and others except #1 one. Should I send v2 which only have first patch? Thanks Chin Liang > > > Signed-off-by: Chin Liang See <clsee@altera.com> > > --- > > board/altera/arria5-socdk/qts/sdram_config.h | 3 +++ > > board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++ > > 2 files changed, 6 insertions(+) > > > > diff --git a/board/altera/arria5-socdk/qts/sdram_config.h > > b/board/altera/arria5-socdk/qts/sdram_config.h > > index e9fe60f..8964637 100644 > > --- a/board/altera/arria5-socdk/qts/sdram_config.h > > +++ b/board/altera/arria5-socdk/qts/sdram_config.h > > @@ -49,6 +49,9 @@ > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP > > 4 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT > > 3 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT > > 512 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C > > HIP 2 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST > > 0 > > diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h > > b/board/altera/cyclone5-socdk/qts/sdram_config.h > > index 37c1476..1bc6f6f 100644 > > --- a/board/altera/cyclone5-socdk/qts/sdram_config.h > > +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h > > @@ -49,6 +49,9 @@ > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP > > 3 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT > > 3 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT > > 512 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C > > HIP 2 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST > > 0 > > > >
On 09/15/2016 09:27 AM, Chin Liang See wrote: > Adding new handoff for SDRAM ctrcfg.extratime1 which is > required for stabil LPDDR2 operation ... stable ... Isn't SoCDK using DDR3 DRAM ? > Signed-off-by: Chin Liang See <clsee@altera.com> > --- > board/altera/arria5-socdk/qts/sdram_config.h | 3 +++ > board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h > index e9fe60f..8964637 100644 > --- a/board/altera/arria5-socdk/qts/sdram_config.h > +++ b/board/altera/arria5-socdk/qts/sdram_config.h > @@ -49,6 +49,9 @@ > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 > diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h > index 37c1476..1bc6f6f 100644 > --- a/board/altera/cyclone5-socdk/qts/sdram_config.h > +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h > @@ -49,6 +49,9 @@ > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 >
On 09/19/2016 12:12 PM, Chin Liang See wrote: > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: >> On 09/15/2016 09:27 AM, Chin Liang See wrote: >>> Adding new handoff for SDRAM ctrcfg.extratime1 which is >>> required for stabil LPDDR2 operation >> >> ... stable ... >> >> Isn't SoCDK using DDR3 DRAM ? > > Yah, you are right where we won't need this patch and others except #1 > one. Should I send v2 which only have first patch? Then should this register be set to zero on SoCDK ?
On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote: > On 09/19/2016 12:12 PM, Chin Liang See wrote: > > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > > > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > > > Adding new handoff for SDRAM ctrcfg.extratime1 which is > > > > required for stabil LPDDR2 operation > > > > > > ... stable ... > > > > > > Isn't SoCDK using DDR3 DRAM ? > > > > Yah, you are right where we won't need this patch and others except > > #1 > > one. Should I send v2 which only have first patch? > > Then should this register be set to zero on SoCDK ? Not required as the default value is zero. Thanks Chin Liang > >
On 09/20/2016 07:37 AM, Chin Liang See wrote: > On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote: >> On 09/19/2016 12:12 PM, Chin Liang See wrote: >>> On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: >>>> On 09/15/2016 09:27 AM, Chin Liang See wrote: >>>>> Adding new handoff for SDRAM ctrcfg.extratime1 which is >>>>> required for stabil LPDDR2 operation >>>> >>>> ... stable ... >>>> >>>> Isn't SoCDK using DDR3 DRAM ? >>> >>> Yah, you are right where we won't need this patch and others except >>> #1 >>> one. Should I send v2 which only have first patch? >> >> Then should this register be set to zero on SoCDK ? > > Not required as the default value is zero. OK, if we can avoid the ifdef(s)
On Tue, 2016-09-20 at 09:52 +0200, Marek Vasut wrote: > On 09/20/2016 07:37 AM, Chin Liang See wrote: > > On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote: > > > On 09/19/2016 12:12 PM, Chin Liang See wrote: > > > > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > > > > > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > > > > > Adding new handoff for SDRAM ctrcfg.extratime1 which is > > > > > > required for stabil LPDDR2 operation > > > > > > > > > > ... stable ... > > > > > > > > > > Isn't SoCDK using DDR3 DRAM ? > > > > > > > > Yah, you are right where we won't need this patch and others > > > > except > > > > #1 > > > > one. Should I send v2 which only have first patch? > > > > > > Then should this register be set to zero on SoCDK ? > > > > Not required as the default value is zero. > > OK, if we can avoid the ifdef(s) > Removing the ifdef would requiring the patch against all socfpga boards. As commented by you earlier, all our boards are using DDR3 and this patch for LPDDR2 would not applicable then. Thanks Chin Liang
On 09/20/2016 11:13 AM, Chin Liang See wrote: > On Tue, 2016-09-20 at 09:52 +0200, Marek Vasut wrote: >> On 09/20/2016 07:37 AM, Chin Liang See wrote: >>> On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote: >>>> On 09/19/2016 12:12 PM, Chin Liang See wrote: >>>>> On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: >>>>>> On 09/15/2016 09:27 AM, Chin Liang See wrote: >>>>>>> Adding new handoff for SDRAM ctrcfg.extratime1 which is >>>>>>> required for stabil LPDDR2 operation >>>>>> >>>>>> ... stable ... >>>>>> >>>>>> Isn't SoCDK using DDR3 DRAM ? >>>>> >>>>> Yah, you are right where we won't need this patch and others >>>>> except >>>>> #1 >>>>> one. Should I send v2 which only have first patch? >>>> >>>> Then should this register be set to zero on SoCDK ? >>> >>> Not required as the default value is zero. >> >> OK, if we can avoid the ifdef(s) >> > > Removing the ifdef would requiring the patch against all socfpga > boards. As commented by you earlier, all our boards are using DDR3 and > this patch for LPDDR2 would not applicable then. I'm fine if you add another patch which sets the register or it's macros to 0 for all SoCFPGA boards.
diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h index e9fe60f..8964637 100644 --- a/board/altera/arria5-socdk/qts/sdram_config.h +++ b/board/altera/arria5-socdk/qts/sdram_config.h @@ -49,6 +49,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h index 37c1476..1bc6f6f 100644 --- a/board/altera/cyclone5-socdk/qts/sdram_config.h +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h @@ -49,6 +49,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stabil LPDDR2 operation Signed-off-by: Chin Liang See <clsee@altera.com> --- board/altera/arria5-socdk/qts/sdram_config.h | 3 +++ board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++ 2 files changed, 6 insertions(+)