[U-Boot,v3] test/py: Add option to skip SPL signature checking

Provide user option to skip SPL signature verification for cases where
u-boot is build with SPL support but full U-Boot is also verified
without SPL.

If you want to support this feature please add env__spl_skipped = True
to your boardenv configuration file.

For example Xilinx Zynq is using this feature where the same U-Boot
binary is checked with SPL and without SPL(with FSBL).

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v3:
- Remove Stephen's lines
- Fix my misundersting what Stephen was asking for. Use diferent
  variable name but use origin env__spl_skipped board variable name
  which was renamed in v2.

Changes in v2:
- nits in commit message
- Rename to env_spl_skipped from env__spl_skipped

 test/py/u_boot_console_base.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

On Thu, Feb 25, 2016 at 02:58:24PM +0100, Michal Simek wrote:
> Provide user option to skip SPL signature verification for cases where

> u-boot is build with SPL support but full U-Boot is also verified
> without SPL.
> 
> If you want to support this feature please add env__spl_skipped = True
> to your boardenv configuration file.
> 
> For example Xilinx Zynq is using this feature where the same U-Boot
> binary is checked with SPL and without SPL(with FSBL).
> 
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

OK, so I'm quite confused as to why there's this patch and also
https://patchwork.ozlabs.org/patch/584240/ which I am (or was) about to
push (bisecting some patches that had problems, that I had hoped to push
out has delayed me pushing a bunch of things).  Does Heiko's patch also
fix the problem you see?  Is one of these better than the other?
Thanks!

> ---
> 
> Changes in v3:
> - Remove Stephen's lines
> - Fix my misundersting what Stephen was asking for. Use diferent
>   variable name but use origin env__spl_skipped board variable name
>   which was renamed in v2.
> 
> Changes in v2:
> - nits in commit message
> - Rename to env_spl_skipped from env__spl_skipped
> 
>  test/py/u_boot_console_base.py | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
> index d6502c6e64cb..318e28824cc2 100644
> --- a/test/py/u_boot_console_base.py
> +++ b/test/py/u_boot_console_base.py
> @@ -307,7 +307,9 @@ class ConsoleBase(object):
>              config_spl = bcfg.get('config_spl', 'n') == 'y'
>              config_spl_serial_support = bcfg.get('config_spl_serial_support',
>                                                   'n') == 'y'
> -            if config_spl and config_spl_serial_support:
> +            env_spl_skipped = self.config.env.get('env__spl_skipped',
> +                                                  False)
> +            if config_spl and config_spl_serial_support and not env_spl_skipped:
>                  m = self.p.expect([pattern_u_boot_spl_signon] +
>                                    self.bad_patterns)
>                  if m != 0:
> -- 
> 1.9.1
>

Hi Tom,

2016-02-25 15:30 GMT+01:00 Tom Rini <trini@konsulko.com>:

> On Thu, Feb 25, 2016 at 02:58:24PM +0100, Michal Simek wrote:
> > Provide user option to skip SPL signature verification for cases where
>
> > u-boot is build with SPL support but full U-Boot is also verified
> > without SPL.
> >
> > If you want to support this feature please add env__spl_skipped = True
> > to your boardenv configuration file.
> >
> > For example Xilinx Zynq is using this feature where the same U-Boot
> > binary is checked with SPL and without SPL(with FSBL).
> >
> > Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>
> OK, so I'm quite confused as to why there's this patch and also
> https://patchwork.ozlabs.org/patch/584240/ which I am (or was) about to
> push (bisecting some patches that had problems, that I had hoped to push
> out has delayed me pushing a bunch of things).  Does Heiko's patch also
> fix the problem you see?  Is one of these better than the other?
> Thanks!


This is based on the top of Heiko patch.
Heiko patch is fixing problem where you have SPL enabled but you don't have
any SPL serial output
which you can't track.
My patch is fixing different problem which is that you have SPL enabled and
SPL serial is also there
but your booting flow has not SPL there. For example testing on QEMU.
Testing without reruning SPL.
Testing the same u-boot elf with different bootloader.
That's why we talked about adding option to user to skip SPL checking via
boardenv file.

Thanks,
Michal

On Thu, Feb 25, 2016 at 02:58:24PM +0100, Michal Simek wrote:

> Provide user option to skip SPL signature verification for cases where
> u-boot is build with SPL support but full U-Boot is also verified
> without SPL.
> 
> If you want to support this feature please add env__spl_skipped = True
> to your boardenv configuration file.
> 
> For example Xilinx Zynq is using this feature where the same U-Boot
> binary is checked with SPL and without SPL(with FSBL).
> 
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Applied to u-boot/master, thanks!

On 02/25/2016 06:58 AM, Michal Simek wrote:
> Provide user option to skip SPL signature verification for cases where
> u-boot is build with SPL support but full U-Boot is also verified
> without SPL.
>
> If you want to support this feature please add env__spl_skipped = True
> to your boardenv configuration file.
>
> For example Xilinx Zynq is using this feature where the same U-Boot
> binary is checked with SPL and without SPL(with FSBL).

Acked-by: Stephen Warren <swarren@nvidia.com>