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GET /api/patches/956001/?format=api
{ "id": 956001, "url": "http://patchwork.ozlabs.org/api/patches/956001/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-42-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180810060711.6547-42-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2018-08-10T06:06:59", "name": "[U-Boot,v2,41/53] clk: sunxi: Implement UART clocks", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "6069da4c41c661ea02acfad62b3da8ab58acb9e3", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 17739, "url": "http://patchwork.ozlabs.org/api/users/17739/?format=api", "username": "jagan", "first_name": "Jagannadha Sutradharudu", "last_name": "Teki", "email": "jagannadh.teki@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20180810060711.6547-42-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 60190, "url": "http://patchwork.ozlabs.org/api/series/60190/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=60190", "date": "2018-08-10T06:06:18", "name": "clk: Add Allwinner CLK, RESET support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/60190/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/956001/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/956001/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"EAa/vDFd\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 41mwV10SjGz9s7Q\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 10 Aug 2018 16:40:08 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 86F8EC21C51; Fri, 10 Aug 2018 06:26:21 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 0E5C3C21F00;\n\tFri, 10 Aug 2018 06:17:05 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=pGfdArz2K3ge8obduPw8mUyU2HZ31EM+wEYQFwaEGc4=;\n\tb=sW3qJE6Hi7J1ol3pQSnXiTl01Zx2FfylodqZKoBpk7t0P+LleNw6DEU0tNsOFRTgrf\n\tIz0TaEOcwQM3UL9xnDyWkObPvZcioIR8QYT2xDQwxF074zuLYttGmnsd8ts3IAky+Xpj\n\tW3zI1GJWVVo8Og9s3LJEKNplnuYE0Gndyvv/+sSGECUAA24TRhrseJTALVlx64QoTgbe\n\tjSdvTvgUSCT6TzYFduTXpSY6WHtsM1i0ICbn0QgrEJtLbtuRs6TO22elUu8RdqYuz0Bf\n\tXWuKc5Y7Jr+2eLqTWEvs39WXtXF/vyAhXNbz1uHzTfC+ML6ZiWG8L/3lglVZxOoG1Syk\n\tcfdg==", "X-Gm-Message-State": "AOUpUlFNPxF0iA2ynwXziNObacnPu3U0PdnGdg1JnsKpF7PFjf0LiNo/\n\t/VvULqGtRYE3ZagQTpJ0X7KqRw==", "X-Google-Smtp-Source": "AA+uWPyKUKDYOvVVOEUHS2/Uh0jd70yef7LuD8dwLDC/DChfuiaCwNVUXWUp5NXqKdbqELfVZajyTg==", "X-Received": "by 2002:a62:9bc5:: with SMTP id\n\te66-v6mr5576106pfk.84.1533881414332; \n\tThu, 09 Aug 2018 23:10:14 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Maxime Ripard <maxime.ripard@bootlin.com>,\n\tAndre Przywara <andre.przywara@arm.com>, Chen-Yu Tsai <wens@csie.org>,\n\tIcenowy Zheng <icenowy@aosc.io>", "Date": "Fri, 10 Aug 2018 11:36:59 +0530", "Message-Id": "<20180810060711.6547-42-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "References": "<20180810060711.6547-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "Tom Rini <trini@konsulko.com>, u-boot@lists.denx.de", "Subject": "[U-Boot] [PATCH v2 41/53] clk: sunxi: Implement UART clocks", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Implement UART clocks for all Allwinner SoC\nclock drivers via clock map descriptor table.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/clk/sunxi/clk_a10.c | 9 +++++++++\n drivers/clk/sunxi/clk_a10s.c | 5 +++++\n drivers/clk/sunxi/clk_a23.c | 6 ++++++\n drivers/clk/sunxi/clk_a31.c | 7 +++++++\n drivers/clk/sunxi/clk_a64.c | 6 ++++++\n drivers/clk/sunxi/clk_a83t.c | 6 ++++++\n drivers/clk/sunxi/clk_h3.c | 5 +++++\n drivers/clk/sunxi/clk_r40.c | 9 +++++++++\n drivers/clk/sunxi/clk_v3s.c | 4 ++++\n 9 files changed, 57 insertions(+)", "diff": "diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c\nindex ee499c402a..d145d37217 100644\n--- a/drivers/clk/sunxi/clk_a10.c\n+++ b/drivers/clk/sunxi/clk_a10.c\n@@ -27,6 +27,15 @@ static struct ccu_clk_map a10_clks[] = {\n \t[CLK_AHB_SPI2]\t\t= { 0x060, BIT(22), NULL },\n \t[CLK_AHB_SPI3]\t\t= { 0x060, BIT(23), NULL },\n \n+\t[CLK_APB1_UART0]\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_APB1_UART1]\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_APB1_UART2]\t= { 0x06c, BIT(18), NULL },\n+\t[CLK_APB1_UART3]\t= { 0x06c, BIT(19), NULL },\n+\t[CLK_APB1_UART4]\t= { 0x06c, BIT(20), NULL },\n+\t[CLK_APB1_UART5]\t= { 0x06c, BIT(21), NULL },\n+\t[CLK_APB1_UART6]\t= { 0x06c, BIT(22), NULL },\n+\t[CLK_APB1_UART7]\t= { 0x06c, BIT(23), NULL },\n+\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\ndiff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c\nindex bca248f59f..5912043f19 100644\n--- a/drivers/clk/sunxi/clk_a10s.c\n+++ b/drivers/clk/sunxi/clk_a10s.c\n@@ -23,6 +23,11 @@ static struct ccu_clk_map a10s_clks[] = {\n \t[CLK_AHB_SPI1]\t\t= { 0x060, BIT(21), NULL },\n \t[CLK_AHB_SPI2]\t\t= { 0x060, BIT(22), NULL },\n \n+\t[CLK_APB1_UART0]\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_APB1_UART1]\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_APB1_UART2]\t= { 0x06c, BIT(18), NULL },\n+\t[CLK_APB1_UART3]\t= { 0x06c, BIT(19), NULL },\n+\n #ifdef CONFIG_MMC\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\ndiff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c\nindex 183c6275f3..331c79af81 100644\n--- a/drivers/clk/sunxi/clk_a23.c\n+++ b/drivers/clk/sunxi/clk_a23.c\n@@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = {\n \t[CLK_BUS_EHCI]\t\t= { 0x060, BIT(26), NULL },\n \t[CLK_BUS_OHCI]\t\t= { 0x060, BIT(29), NULL },\n \n+\t[CLK_BUS_UART0]\t\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_BUS_UART1]\t\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_BUS_UART2]\t\t= { 0x06c, BIT(18), NULL },\n+\t[CLK_BUS_UART3]\t\t= { 0x06c, BIT(19), NULL },\n+\t[CLK_BUS_UART4]\t\t= { 0x06c, BIT(20), NULL },\n+\n #ifdef CONFIG_MMC\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\ndiff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c\nindex a5c6628c63..40803a1d64 100644\n--- a/drivers/clk/sunxi/clk_a31.c\n+++ b/drivers/clk/sunxi/clk_a31.c\n@@ -28,6 +28,13 @@ static struct ccu_clk_map a31_clks[] = {\n \t[CLK_AHB1_OHCI1]\t= { 0x060, BIT(30), NULL },\n \t[CLK_AHB1_OHCI2]\t= { 0x060, BIT(31), NULL },\n \n+\t[CLK_APB2_UART0]\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_APB2_UART1]\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_APB2_UART2]\t= { 0x06c, BIT(18), NULL },\n+\t[CLK_APB2_UART3]\t= { 0x06c, BIT(19), NULL },\n+\t[CLK_APB2_UART4]\t= { 0x06c, BIT(20), NULL },\n+\t[CLK_APB2_UART5]\t= { 0x06c, BIT(21), NULL },\n+\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\ndiff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c\nindex 218d4f09ea..13b506f983 100644\n--- a/drivers/clk/sunxi/clk_a64.c\n+++ b/drivers/clk/sunxi/clk_a64.c\n@@ -24,6 +24,12 @@ static struct ccu_clk_map a64_clks[] = {\n \t[CLK_BUS_OHCI0]\t\t= { 0x060, BIT(28), NULL },\n \t[CLK_BUS_OHCI1]\t\t= { 0x060, BIT(29), NULL },\n \n+\t[CLK_BUS_UART0]\t\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_BUS_UART1]\t\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_BUS_UART2]\t\t= { 0x06c, BIT(18), NULL },\n+\t[CLK_BUS_UART3]\t\t= { 0x06c, BIT(19), NULL },\n+\t[CLK_BUS_UART4]\t\t= { 0x06c, BIT(20), NULL },\n+\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\ndiff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c\nindex 47b7672e7f..5c1235fa7b 100644\n--- a/drivers/clk/sunxi/clk_a83t.c\n+++ b/drivers/clk/sunxi/clk_a83t.c\n@@ -21,6 +21,12 @@ static struct ccu_clk_map a83t_clks[] = {\n \t[CLK_BUS_EHCI1]\t\t= { 0x060, BIT(27), NULL },\n \t[CLK_BUS_OHCI0]\t\t= { 0x060, BIT(29), NULL },\n \n+\t[CLK_BUS_UART0]\t\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_BUS_UART1]\t\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_BUS_UART2]\t\t= { 0x06c, BIT(18), NULL },\n+\t[CLK_BUS_UART3]\t\t= { 0x06c, BIT(19), NULL },\n+\t[CLK_BUS_UART4]\t\t= { 0x06c, BIT(20), NULL },\n+\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\ndiff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c\nindex f610cee745..b132ae0a0d 100644\n--- a/drivers/clk/sunxi/clk_h3.c\n+++ b/drivers/clk/sunxi/clk_h3.c\n@@ -28,6 +28,11 @@ static struct ccu_clk_map h3_clks[] = {\n \t[CLK_BUS_OHCI2]\t\t= { 0x060, BIT(30), NULL },\n \t[CLK_BUS_OHCI3]\t\t= { 0x060, BIT(31), NULL },\n \n+\t[CLK_BUS_UART0]\t\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_BUS_UART1]\t\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_BUS_UART2]\t\t= { 0x06c, BIT(18), NULL },\n+\t[CLK_BUS_UART3]\t\t= { 0x06c, BIT(19), NULL },\n+\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\ndiff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c\nindex 24c26ad3be..1e5b1d10f7 100644\n--- a/drivers/clk/sunxi/clk_r40.c\n+++ b/drivers/clk/sunxi/clk_r40.c\n@@ -25,6 +25,15 @@ static struct ccu_clk_map r40_clks[] = {\n \t[CLK_BUS_OHCI1]\t\t= { 0x060, BIT(30), NULL },\n \t[CLK_BUS_OHCI2]\t\t= { 0x060, BIT(31), NULL },\n \n+\t[CLK_BUS_UART0]\t\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_BUS_UART1]\t\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_BUS_UART2]\t\t= { 0x06c, BIT(18), NULL },\n+\t[CLK_BUS_UART3]\t\t= { 0x06c, BIT(19), NULL },\n+\t[CLK_BUS_UART4]\t\t= { 0x06c, BIT(20), NULL },\n+\t[CLK_BUS_UART5]\t\t= { 0x06c, BIT(21), NULL },\n+\t[CLK_BUS_UART6]\t\t= { 0x06c, BIT(22), NULL },\n+\t[CLK_BUS_UART7]\t\t= { 0x06c, BIT(23), NULL },\n+\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\ndiff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c\nindex ae4f6ee066..c6e57147ee 100644\n--- a/drivers/clk/sunxi/clk_v3s.c\n+++ b/drivers/clk/sunxi/clk_v3s.c\n@@ -19,6 +19,10 @@ static struct ccu_clk_map v3s_clks[] = {\n \t[CLK_BUS_SPI0]\t\t= { 0x060, BIT(20), NULL },\n \t[CLK_BUS_OTG]\t\t= { 0x060, BIT(24), NULL },\n \n+\t[CLK_BUS_UART0]\t\t= { 0x06c, BIT(16), NULL },\n+\t[CLK_BUS_UART1]\t\t= { 0x06c, BIT(17), NULL },\n+\t[CLK_BUS_UART2]\t\t= { 0x06c, BIT(18), NULL },\n+\n \t[CLK_MMC0]\t\t= { 0x088, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC1]\t\t= { 0x08c, BIT(31), &mmc_clk_set_rate },\n \t[CLK_MMC2]\t\t= { 0x090, BIT(31), &mmc_clk_set_rate },\n", "prefixes": [ "U-Boot", "v2", "41/53" ] }