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GET /api/patches/819236/?format=api
{ "id": 819236, "url": "http://patchwork.ozlabs.org/api/patches/819236/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170927170027.8539-2-david@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170927170027.8539-2-david@redhat.com>", "list_archive_url": null, "date": "2017-09-27T17:00:25", "name": "[RFC,1/3] accel/tcg: allow to invalidate a write TLB entry immediately", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "40df43cbe8625c2632da637d90a3140fec0710f8", "submitter": { "id": 70402, "url": "http://patchwork.ozlabs.org/api/people/70402/?format=api", "name": "David Hildenbrand", "email": "david@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170927170027.8539-2-david@redhat.com/mbox/", "series": [ { "id": 5406, "url": "http://patchwork.ozlabs.org/api/series/5406/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=5406", "date": "2017-09-27T17:00:24", "name": "s390x/tcg: LAP support using immediate TLB invalidation", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/5406/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/819236/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/819236/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ext-mx06.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com", "ext-mx06.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=david@redhat.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2PH55SS4z9tXb\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 28 Sep 2017 03:01:21 +1000 (AEST)", "from localhost ([::1]:55620 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dxFi3-0006fV-TK\n\tfor incoming@patchwork.ozlabs.org; Wed, 27 Sep 2017 13:01:19 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:60016)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <david@redhat.com>) id 1dxFhU-0006bM-33\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:00:49 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <david@redhat.com>) id 1dxFhQ-00064n-0r\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:00:44 -0400", "from mx1.redhat.com ([209.132.183.28]:46742)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <david@redhat.com>) id 1dxFhP-00064E-Ou\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:00:39 -0400", "from smtp.corp.redhat.com\n\t(int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 9BF0A3A58B6;\n\tWed, 27 Sep 2017 17:00:38 +0000 (UTC)", "from t460s.redhat.com (ovpn-117-241.ams2.redhat.com\n\t[10.36.117.241])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 5BB8AE8184;\n\tWed, 27 Sep 2017 17:00:30 +0000 (UTC)" ], "DMARC-Filter": "OpenDMARC Filter v1.3.2 mx1.redhat.com 9BF0A3A58B6", "From": "David Hildenbrand <david@redhat.com>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 27 Sep 2017 19:00:25 +0200", "Message-Id": "<20170927170027.8539-2-david@redhat.com>", "In-Reply-To": "<20170927170027.8539-1-david@redhat.com>", "References": "<20170927170027.8539-1-david@redhat.com>", "X-Scanned-By": "MIMEDefang 2.79 on 10.5.11.13", "X-Greylist": "Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.30]);\n\tWed, 27 Sep 2017 17:00:38 +0000 (UTC)", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "209.132.183.28", "Subject": "[Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a write\n\tTLB entry immediately", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "thuth@redhat.com, David Hildenbrand <david@redhat.com>, cohuck@redhat.com,\n\tRichard Henderson <richard.henderson@linaro.org>,\n\tAlexander Graf <agraf@suse.de>,\n\tChristian Borntraeger <borntraeger@de.ibm.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Background: s390x implements Low-Address Protection (LAP). If LAP is\nenabled, writing to effective addresses (before any transaltion)\n0-511 and 4096-4607 triggers a protection exception.\n\nSo we have subpage protection on the first two pages of every address\nspace (where the lowcore - the CPU private data resides).\n\nBy immediately invalidating the write entry but allowing the caller to\ncontinue, we force every write access onto these first two pages into\nthe slow path. we will get a tlb fault with the specific accessed\naddresses and can then evaluate if protection applies or not.\n\nWe have to make sure to ignore the invalid bit if tlb_fill() succeeds.\n\nSigned-off-by: David Hildenbrand <david@redhat.com>\n---\n accel/tcg/cputlb.c | 5 ++++-\n accel/tcg/softmmu_template.h | 4 ++--\n include/exec/cpu-all.h | 3 +++\n 3 files changed, 9 insertions(+), 3 deletions(-)", "diff": "diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c\nindex bcbcc4db6c..5bc4233961 100644\n--- a/accel/tcg/cputlb.c\n+++ b/accel/tcg/cputlb.c\n@@ -683,6 +683,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,\n } else {\n tn.addr_write = address;\n }\n+ if (prot & PAGE_WRITE_INV) {\n+ tn.addr_write |= TLB_INVALID_MASK;\n+ }\n }\n \n /* Pairs with flag setting in tlb_reset_dirty_range */\n@@ -967,7 +970,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,\n if (!VICTIM_TLB_HIT(addr_write, addr)) {\n tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);\n }\n- tlb_addr = tlbe->addr_write;\n+ tlb_addr = tlbe->addr_write & ~TLB_INVALID_MASK;\n }\n \n /* Check notdirty */\ndiff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h\nindex d7563292a5..3fc5144316 100644\n--- a/accel/tcg/softmmu_template.h\n+++ b/accel/tcg/softmmu_template.h\n@@ -285,7 +285,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,\n if (!VICTIM_TLB_HIT(addr_write, addr)) {\n tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);\n }\n- tlb_addr = env->tlb_table[mmu_idx][index].addr_write;\n+ tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK;\n }\n \n /* Handle an IO access. */\n@@ -361,7 +361,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,\n if (!VICTIM_TLB_HIT(addr_write, addr)) {\n tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);\n }\n- tlb_addr = env->tlb_table[mmu_idx][index].addr_write;\n+ tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK;\n }\n \n /* Handle an IO access. */\ndiff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h\nindex ffe43d5654..24b9509604 100644\n--- a/include/exec/cpu-all.h\n+++ b/include/exec/cpu-all.h\n@@ -247,6 +247,9 @@ extern intptr_t qemu_host_page_mask;\n /* original state of the write flag (used when tracking self-modifying\n code */\n #define PAGE_WRITE_ORG 0x0010\n+/* Invalidate the TLB entry immediately, helpful for s390x\n+ * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */\n+#define PAGE_WRITE_INV 0x0040\n #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)\n /* FIXME: Code that sets/uses this is broken and needs to go away. */\n #define PAGE_RESERVED 0x0020\n", "prefixes": [ "RFC", "1/3" ] }