[{"id":1776499,"web_url":"http://patchwork.ozlabs.org/comment/1776499/","msgid":"<30b6f3a1-bfeb-6172-5233-2f7d444399fc@linaro.org>","list_archive_url":null,"date":"2017-09-27T17:48:39","subject":"Re: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a\n\twrite TLB entry immediately","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/27/2017 10:00 AM, David Hildenbrand wrote:\n> Background: s390x implements Low-Address Protection (LAP). If LAP is\n> enabled, writing to effective addresses (before any transaltion)\n> 0-511 and 4096-4607 triggers a protection exception.\n> \n> So we have subpage protection on the first two pages of every address\n> space (where the lowcore - the CPU private data resides).\n> \n> By immediately invalidating the write entry but allowing the caller to\n> continue, we force every write access onto these first two pages into\n> the slow path. we will get a tlb fault with the specific accessed\n> addresses and can then evaluate if protection applies or not.\n> \n> We have to make sure to ignore the invalid bit if tlb_fill() succeeds.\n\nThis is similar to a scheme I proposed to PMM wrt handling ARM v8M translation.\n Reusing TLB_INVALID_MASK would appear to work, but I wonder if it wouldn't be\nclearer to use another bit. I believe I had proposed a TLB_FORCE_SLOW_MASK.\n\nThoughts, Peter?\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"BHtp4SZS\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2QLN3D8zz9sNV\n\tfor ;\n\tThu, 28 Sep 2017 03:49:15 +1000 (AEST)","from localhost ([::1]:55781 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dxGSN-0003R6-N7\n\tfor incoming@patchwork.ozlabs.org; Wed, 27 Sep 2017 13:49:11 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43583)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dxGS1-0003Qy-Pt\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:48:50 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dxGRw-0003v3-BB\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:48:49 -0400","from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:43607)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dxGRw-0003uV-5F\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 13:48:44 -0400","by mail-pf0-x229.google.com with SMTP id y29so7618973pff.0\n\tfor ; Wed, 27 Sep 2017 10:48:43 -0700 (PDT)","from bigtime.twiddle.net ([70.35.39.2])\n\tby smtp.gmail.com with ESMTPSA id\n\te7sm21049052pfi.188.2017.09.27.10.48.41\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 27 Sep 2017 10:48:41 -0700 (PDT)"],"DKIM-Signature":"v=1; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170927170027.8539-2-david@redhat.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::229","Subject":"Re: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a\n\twrite TLB entry immediately","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Christian Borntraeger , thuth@redhat.com,\n\tcohuck@redhat.com, Alexander Graf ,\n\tPeter Maydell ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1776538,"web_url":"http://patchwork.ozlabs.org/comment/1776538/","msgid":"","list_archive_url":null,"date":"2017-09-27T18:50:22","subject":"Re: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a\n\twrite TLB entry immediately","submitter":{"id":70402,"url":"http://patchwork.ozlabs.org/api/people/70402/","name":"David Hildenbrand","email":"david@redhat.com"},"content":"On 27.09.2017 19:48, Richard Henderson wrote:\n> On 09/27/2017 10:00 AM, David Hildenbrand wrote:\n>> Background: s390x implements Low-Address Protection (LAP). If LAP is\n>> enabled, writing to effective addresses (before any transaltion)\n>> 0-511 and 4096-4607 triggers a protection exception.\n>>\n>> So we have subpage protection on the first two pages of every address\n>> space (where the lowcore - the CPU private data resides).\n>>\n>> By immediately invalidating the write entry but allowing the caller to\n>> continue, we force every write access onto these first two pages into\n>> the slow path. we will get a tlb fault with the specific accessed\n>> addresses and can then evaluate if protection applies or not.\n>>\n>> We have to make sure to ignore the invalid bit if tlb_fill() succeeds.\n> \n> This is similar to a scheme I proposed to PMM wrt handling ARM v8M translation.\n> Reusing TLB_INVALID_MASK would appear to work, but I wonder if it wouldn't be\n> clearer to use another bit. I believe I had proposed a TLB_FORCE_SLOW_MASK.\n\nThe only downside of another bit is that we have to duplicate all\nchecks. Using TLB_INVALID_MASK avoids this change (because it simply works).\n\nOf course, we could come up with something as simple as\n\n#define TLB_INVALID_MASK (TLB_INVALID | TLB_FORCE_SLOW)\n\nand fixup the few places where TLB_INVALID_MASK really just has to be\nTLB_INVALID.\n\nHave no strong opinion on this. This way requires minimal changes.\n\n> \n> Thoughts, Peter?\n> \n> \n> r~\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx05.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=david@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2RjS74skz9tXp\n\tfor ;\n\tThu, 28 Sep 2017 04:50:52 +1000 (AEST)","from localhost ([::1]:55950 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dxHQ3-0006lN-2H\n\tfor incoming@patchwork.ozlabs.org; Wed, 27 Sep 2017 14:50:51 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:57029)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dxHPj-0006l7-2V\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 14:50:31 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dxHPf-0002lH-5X\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 14:50:31 -0400","from mx1.redhat.com ([209.132.183.28]:50792)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dxHPe-0002ky-PS\n\tfor qemu-devel@nongnu.org; Wed, 27 Sep 2017 14:50:27 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id BB854437F56;\n\tWed, 27 Sep 2017 18:50:25 +0000 (UTC)","from [10.36.116.69] (ovpn-116-69.ams2.redhat.com [10.36.116.69])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 7F0C088E26;\n\tWed, 27 Sep 2017 18:50:23 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com BB854437F56","To":"Richard Henderson , qemu-devel@nongnu.org","References":"<20170927170027.8539-1-david@redhat.com>\n\t<20170927170027.8539-2-david@redhat.com>\n\t<30b6f3a1-bfeb-6172-5233-2f7d444399fc@linaro.org>","From":"David Hildenbrand ","Organization":"Red Hat GmbH","Message-ID":"","Date":"Wed, 27 Sep 2017 20:50:22 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<30b6f3a1-bfeb-6172-5233-2f7d444399fc@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.29]);\n\tWed, 27 Sep 2017 18:50:25 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a\n\twrite TLB entry immediately","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Christian Borntraeger , thuth@redhat.com,\n\tcohuck@redhat.com, Alexander Graf ,\n\tPeter Maydell ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1787190,"web_url":"http://patchwork.ozlabs.org/comment/1787190/","msgid":"","list_archive_url":null,"date":"2017-10-16T07:24:47","subject":"Re: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a\n\twrite TLB entry immediately","submitter":{"id":70402,"url":"http://patchwork.ozlabs.org/api/people/70402/","name":"David Hildenbrand","email":"david@redhat.com"},"content":"On 27.09.2017 19:48, Richard Henderson wrote:\n> On 09/27/2017 10:00 AM, David Hildenbrand wrote:\n>> Background: s390x implements Low-Address Protection (LAP). If LAP is\n>> enabled, writing to effective addresses (before any transaltion)\n>> 0-511 and 4096-4607 triggers a protection exception.\n>>\n>> So we have subpage protection on the first two pages of every address\n>> space (where the lowcore - the CPU private data resides).\n>>\n>> By immediately invalidating the write entry but allowing the caller to\n>> continue, we force every write access onto these first two pages into\n>> the slow path. we will get a tlb fault with the specific accessed\n>> addresses and can then evaluate if protection applies or not.\n>>\n>> We have to make sure to ignore the invalid bit if tlb_fill() succeeds.\n> \n> This is similar to a scheme I proposed to PMM wrt handling ARM v8M translation.\n> Reusing TLB_INVALID_MASK would appear to work, but I wonder if it wouldn't be\n> clearer to use another bit. I believe I had proposed a TLB_FORCE_SLOW_MASK.\n> \n> Thoughts, Peter?\n\nAs two weeks have passed:\n\nAny further opinions? Richard, how do you want me to continue with this?\n\nThanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=david@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yFqbb64Flz9t1t\n\tfor ;\n\tMon, 16 Oct 2017 18:25:14 +1100 (AEDT)","from localhost ([::1]:59747 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e3zlw-0000UV-7b\n\tfor incoming@patchwork.ozlabs.org; Mon, 16 Oct 2017 03:25:12 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52169)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1e3zle-0000UP-Q9\n\tfor qemu-devel@nongnu.org; Mon, 16 Oct 2017 03:24:55 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1e3zlb-0007dv-Mo\n\tfor qemu-devel@nongnu.org; Mon, 16 Oct 2017 03:24:54 -0400","from mx1.redhat.com ([209.132.183.28]:41616)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1e3zlb-0007dV-GZ\n\tfor qemu-devel@nongnu.org; Mon, 16 Oct 2017 03:24:51 -0400","from smtp.corp.redhat.com\n\t(int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 6423C81DEA;\n\tMon, 16 Oct 2017 07:24:50 +0000 (UTC)","from [10.36.116.255] (unknown [10.36.116.255])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id D28AD60E3A;\n\tMon, 16 Oct 2017 07:24:48 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 6423C81DEA","To":"Richard Henderson , qemu-devel@nongnu.org","References":"<20170927170027.8539-1-david@redhat.com>\n\t<20170927170027.8539-2-david@redhat.com>\n\t<30b6f3a1-bfeb-6172-5233-2f7d444399fc@linaro.org>","From":"David Hildenbrand ","Organization":"Red Hat GmbH","Message-ID":"","Date":"Mon, 16 Oct 2017 09:24:47 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<30b6f3a1-bfeb-6172-5233-2f7d444399fc@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.12","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.25]);\n\tMon, 16 Oct 2017 07:24:50 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a\n\twrite TLB entry immediately","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Christian Borntraeger , thuth@redhat.com,\n\tcohuck@redhat.com, Alexander Graf ,\n\tPeter Maydell ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1787638,"web_url":"http://patchwork.ozlabs.org/comment/1787638/","msgid":"<1d995492-dbcf-7466-0ebc-9e507d50d099@linaro.org>","list_archive_url":null,"date":"2017-10-16T18:06:49","subject":"Re: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a\n\twrite TLB entry immediately","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 10/16/2017 12:24 AM, David Hildenbrand wrote:\n> On 27.09.2017 19:48, Richard Henderson wrote:\n>> On 09/27/2017 10:00 AM, David Hildenbrand wrote:\n>>> Background: s390x implements Low-Address Protection (LAP). If LAP is\n>>> enabled, writing to effective addresses (before any transaltion)\n>>> 0-511 and 4096-4607 triggers a protection exception.\n>>>\n>>> So we have subpage protection on the first two pages of every address\n>>> space (where the lowcore - the CPU private data resides).\n>>>\n>>> By immediately invalidating the write entry but allowing the caller to\n>>> continue, we force every write access onto these first two pages into\n>>> the slow path. we will get a tlb fault with the specific accessed\n>>> addresses and can then evaluate if protection applies or not.\n>>>\n>>> We have to make sure to ignore the invalid bit if tlb_fill() succeeds.\n>>\n>> This is similar to a scheme I proposed to PMM wrt handling ARM v8M translation.\n>> Reusing TLB_INVALID_MASK would appear to work, but I wonder if it wouldn't be\n>> clearer to use another bit. I believe I had proposed a TLB_FORCE_SLOW_MASK.\n>>\n>> Thoughts, Peter?\n> \n> As two weeks have passed:\n> \n> Any further opinions? Richard, how do you want me to continue with this?\n\nLet's just go ahead with TLB_INVALID_MASK; we'll revisit if it gets to be\nconfusing.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"QQ6Ct2MD\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yG62K2rfpz9t38\n\tfor ;\n\tTue, 17 Oct 2017 05:15:53 +1100 (AEDT)","from localhost ([::1]:34544 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e49sQ-0007go-GG\n\tfor incoming@patchwork.ozlabs.org; Mon, 16 Oct 2017 14:12:34 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:38173)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1e49mz-0003OP-Hu\n\tfor qemu-devel@nongnu.org; Mon, 16 Oct 2017 14:06:59 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1e49mw-0007ye-22\n\tfor qemu-devel@nongnu.org; Mon, 16 Oct 2017 14:06:57 -0400","from mail-pg0-x22b.google.com ([2607:f8b0:400e:c05::22b]:55640)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1e49mv-0007yF-Sx\n\tfor qemu-devel@nongnu.org; Mon, 16 Oct 2017 14:06:53 -0400","by mail-pg0-x22b.google.com with SMTP id b11so7431997pgn.12\n\tfor ; Mon, 16 Oct 2017 11:06:53 -0700 (PDT)","from cloudburst.twiddle.net (97-126-104-76.tukw.qwest.net.\n\t[97.126.104.76]) by smtp.gmail.com with ESMTPSA id\n\tb27sm15565196pfc.110.2017.10.16.11.06.51\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 16 Oct 2017 11:06:51 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=xUO0qTs5ZnsyqF0bqw7j9EQaM0M7JTVF9681TgdSdyc=;\n\tb=QQ6Ct2MDrQIXVjtV4+dZ49LeZeaGz9Ot8h37w8Rws36wpkNiTGmvFt9E2f6b7un88W\n\tiijkq3QGmW7riG40wH5zxx4YAOQj443ehVwFSw5yrS9SBH8+IKtBsGBAC1Ar1NKiZCUt\n\tfOWlyfKruQ/0CR/g9LWsoftu7qxTaxtpdCbIE=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=xUO0qTs5ZnsyqF0bqw7j9EQaM0M7JTVF9681TgdSdyc=;\n\tb=f3j1I6u16bmj6qEhaMaLu7v+cAIageZs8PnYFyvLygOgnbURDFNKWPKMZWGwM5eh7/\n\tTTjTXbFwD6PWAejZqaw4fXrx/B+vG2kuOYAJbboEgbmi1q97LEf9Re5sceQYHAAhxD6I\n\tAC9/VuhLBDpxyj40QDgtMBd/q2E8I7CuHqQQBpDADbH862H3vykpf5ZUK/PH2iTuyY3t\n\tsiIOZmlEgC0L7765oMngqOwNVNjh0m1jBUqH8Dz3RaeN31l4JjwLvmOplYUqtglhlR9h\n\tl6utvq7Fj/oa4wfaoeVag2K9I6ZQp2uGXxlHRVbt1NIElVVRogxWl96oujI6yplBvt5T\n\tWnsQ==","X-Gm-Message-State":"AMCzsaWCACphQCjC+XWX92D+rofM1/8Cmw4L7cVfRyqCyLHll1ahhy5F\n\tbX+Yhn59/DUL+R8ScEHHzYHjAQ==","X-Google-Smtp-Source":"AOwi7QBlPBh4+w9mTYTFzws8RJ0KFFca2AH7NE3HYMJ+6bPpK2BGHCoMs8F9tpt/a/GeGilGd6QWqQ==","X-Received":"by 10.99.115.21 with SMTP id o21mr8691681pgc.265.1508177212736; \n\tMon, 16 Oct 2017 11:06:52 -0700 (PDT)","To":"David Hildenbrand , qemu-devel@nongnu.org","References":"<20170927170027.8539-1-david@redhat.com>\n\t<20170927170027.8539-2-david@redhat.com>\n\t<30b6f3a1-bfeb-6172-5233-2f7d444399fc@linaro.org>\n\t","From":"Richard Henderson ","Message-ID":"<1d995492-dbcf-7466-0ebc-9e507d50d099@linaro.org>","Date":"Mon, 16 Oct 2017 11:06:49 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c05::22b","Subject":"Re: [Qemu-devel] [PATCH RFC 1/3] accel/tcg: allow to invalidate a\n\twrite TLB entry immediately","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Christian Borntraeger , thuth@redhat.com,\n\tcohuck@redhat.com, Alexander Graf ,\n\tPeter Maydell ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]