Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/819166/?format=api
{ "id": 819166, "url": "http://patchwork.ozlabs.org/api/patches/819166/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506519893-16509-4-git-send-email-patrice.chotard@st.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506519893-16509-4-git-send-email-patrice.chotard@st.com>", "list_archive_url": null, "date": "2017-09-27T13:44:50", "name": "[U-Boot,v1,3/6] serial: stm32x7: prepare the ground to STM32F4 support", "commit_ref": "60a996bacb74052f7e3966a875dfdebee036d446", "pull_url": null, "state": "accepted", "archived": false, "hash": "d66d0d328c17a172cf857c51e27f6b4589353533", "submitter": { "id": 63958, "url": "http://patchwork.ozlabs.org/api/people/63958/?format=api", "name": "Patrice CHOTARD", "email": "patrice.chotard@st.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506519893-16509-4-git-send-email-patrice.chotard@st.com/mbox/", "series": [ { "id": 5372, "url": "http://patchwork.ozlabs.org/api/series/5372/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=5372", "date": "2017-09-27T13:44:48", "name": "Update stm32x7 serial driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/5372/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/819166/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/819166/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2JzJ0WQ4z9sRm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 27 Sep 2017 23:47:24 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid D2A8FC21DD7; Wed, 27 Sep 2017 13:46:16 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 89F55C21DD9;\n\tWed, 27 Sep 2017 13:45:13 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid ED1F3C21D64; Wed, 27 Sep 2017 13:45:08 +0000 (UTC)", "from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com\n\t[91.207.212.93])\n\tby lists.denx.de (Postfix) with ESMTPS id B4445C21C4F\n\tfor <u-boot@lists.denx.de>; Wed, 27 Sep 2017 13:45:06 +0000 (UTC)", "from pps.filterd (m0046660.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8RDiCGr014635; Wed, 27 Sep 2017 15:45:02 +0200", "from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2d8d2w010w-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tWed, 27 Sep 2017 15:45:02 +0200", "from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2DB1834;\n\tWed, 27 Sep 2017 13:45:02 +0000 (GMT)", "from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0CEBB28E7;\n\tWed, 27 Sep 2017 13:45:02 +0000 (GMT)", "from localhost (10.75.127.45) by SFHDAG6NODE3.st.com (10.75.127.18)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tWed, 27 Sep 2017 15:45:01 +0200" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "From": "<patrice.chotard@st.com>", "To": "<u-boot@lists.denx.de>, <albert.u.boot@aribaud.net>, <sjg@chromium.org>, \n\t<vikas.manocha@st.com>", "Date": "Wed, 27 Sep 2017 15:44:50 +0200", "Message-ID": "<1506519893-16509-4-git-send-email-patrice.chotard@st.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1506519893-16509-1-git-send-email-patrice.chotard@st.com>", "References": "<1506519893-16509-1-git-send-email-patrice.chotard@st.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.75.127.45]", "X-ClientProxiedBy": "SFHDAG5NODE1.st.com (10.75.127.13) To SFHDAG6NODE3.st.com\n\t(10.75.127.18)", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-27_03:, , signatures=0", "Subject": "[U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to\n\tSTM32F4 support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Patrice Chotard <patrice.chotard@st.com>\n\nSTM32F4 serial IP is similar to F7 and H7, but registers\nare not located at the same offset and some feature are\nonly supported by F7 and H7 version.\n\nRegisters offset must be added for each version and also\nsome flags indicated the supported feature.\n\nUpdate registers name to match with datasheet (sr to isr,\nrx_dr to rdr and tx_dr to tdr) and remove unused regs\n(cr2, gtpr, rtor, and rqr).\n\nSigned-off-by: Patrice Chotard <patrice.chotard@st.com>\n---\n drivers/serial/serial_stm32x7.c | 72 ++++++++++++++++++++++++-----------------\n drivers/serial/serial_stm32x7.h | 38 ++++++++++++++--------\n 2 files changed, 66 insertions(+), 44 deletions(-)", "diff": "diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c\nindex bafcc36..81a2308 100644\n--- a/drivers/serial/serial_stm32x7.c\n+++ b/drivers/serial/serial_stm32x7.c\n@@ -17,67 +17,79 @@ DECLARE_GLOBAL_DATA_PTR;\n \n static int stm32_serial_setbrg(struct udevice *dev, int baudrate)\n {\n-\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n-\tstruct stm32_usart *const usart = plat->base;\n+\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n+\tbool stm32f4 = plat->uart_info->stm32f4;\n+\tfdt_addr_t base = plat->base;\n \tu32 int_div, mantissa, fraction, oversampling;\n \n \tint_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);\n \n \tif (int_div < 16) {\n \t\toversampling = 8;\n-\t\tsetbits_le32(&usart->cr1, USART_CR1_OVER8);\n+\t\tsetbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);\n \t} else {\n \t\toversampling = 16;\n-\t\tclrbits_le32(&usart->cr1, USART_CR1_OVER8);\n+\t\tclrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);\n \t}\n \n \tmantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;\n \tfraction = int_div % oversampling;\n \n-\twritel(mantissa | fraction, &usart->brr);\n+\twritel(mantissa | fraction, base + BRR_OFFSET(stm32f4));\n \n \treturn 0;\n }\n \n static int stm32_serial_getc(struct udevice *dev)\n {\n-\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n-\tstruct stm32_usart *const usart = plat->base;\n+\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n+\tbool stm32f4 = plat->uart_info->stm32f4;\n+\tfdt_addr_t base = plat->base;\n \n-\tif ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)\n+\tif ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)\n \t\treturn -EAGAIN;\n \n-\treturn readl(&usart->rd_dr);\n+\treturn readl(base + RDR_OFFSET(stm32f4));\n }\n \n static int stm32_serial_putc(struct udevice *dev, const char c)\n {\n-\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n-\tstruct stm32_usart *const usart = plat->base;\n+\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n+\tbool stm32f4 = plat->uart_info->stm32f4;\n+\tfdt_addr_t base = plat->base;\n \n-\tif ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)\n+\tif ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)\n \t\treturn -EAGAIN;\n \n-\twritel(c, &usart->tx_dr);\n+\twritel(c, base + TDR_OFFSET(stm32f4));\n \n \treturn 0;\n }\n \n static int stm32_serial_pending(struct udevice *dev, bool input)\n {\n-\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n-\tstruct stm32_usart *const usart = plat->base;\n+\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n+\tbool stm32f4 = plat->uart_info->stm32f4;\n+\tfdt_addr_t base = plat->base;\n \n \tif (input)\n-\t\treturn readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;\n+\t\treturn readl(base + ISR_OFFSET(stm32f4)) &\n+\t\t\tUSART_SR_FLAG_RXNE ? 1 : 0;\n \telse\n-\t\treturn readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;\n+\t\treturn readl(base + ISR_OFFSET(stm32f4)) &\n+\t\t\tUSART_SR_FLAG_TXE ? 0 : 1;\n }\n \n static int stm32_serial_probe(struct udevice *dev)\n {\n-\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n-\tstruct stm32_usart *const usart = plat->base;\n+\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n+\tfdt_addr_t base = plat->base;\n+\tbool stm32f4;\n+\tu8 uart_enable_bit;\n+\n+\tplat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);\n+\tstm32f4 = plat->uart_info->stm32f4;\n+\tuart_enable_bit = plat->uart_info->uart_enable_bit;\n \n #ifdef CONFIG_CLK\n \tint ret;\n@@ -100,32 +112,32 @@ static int stm32_serial_probe(struct udevice *dev)\n \t\treturn plat->clock_rate;\n \t};\n \n-\t/* Disable usart-> disable overrun-> enable usart */\n-\tclrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);\n-\tsetbits_le32(&usart->cr3, USART_CR3_OVRDIS);\n-\tsetbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);\n+\t/* Disable uart-> disable overrun-> enable uart */\n+\tclrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |\n+\t\t BIT(uart_enable_bit));\n+\tif (plat->uart_info->has_overrun_disable)\n+\t\tsetbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);\n+\tsetbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |\n+\t\t BIT(uart_enable_bit));\n \n \treturn 0;\n }\n \n #if CONFIG_IS_ENABLED(OF_CONTROL)\n static const struct udevice_id stm32_serial_id[] = {\n-\t{.compatible = \"st,stm32f7-uart\"},\n-\t{.compatible = \"st,stm32h7-uart\"},\n+\t{ .compatible = \"st,stm32f7-uart\", .data = (ulong)&stm32x7_info},\n+\t{ .compatible = \"st,stm32h7-uart\", .data = (ulong)&stm32x7_info},\n \t{}\n };\n \n static int stm32_serial_ofdata_to_platdata(struct udevice *dev)\n {\n \tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n-\tfdt_addr_t addr;\n \n-\taddr = devfdt_get_addr(dev);\n-\tif (addr == FDT_ADDR_T_NONE)\n+\tplat->base = devfdt_get_addr(dev);\n+\tif (plat->base == FDT_ADDR_T_NONE)\n \t\treturn -EINVAL;\n \n-\tplat->base = (struct stm32_usart *)addr;\n-\n \treturn 0;\n }\n #endif\ndiff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h\nindex 6d36b74..4c6b7d4 100644\n--- a/drivers/serial/serial_stm32x7.h\n+++ b/drivers/serial/serial_stm32x7.h\n@@ -8,30 +8,40 @@\n #ifndef _SERIAL_STM32_X7_\n #define _SERIAL_STM32_X7_\n \n-struct stm32_usart {\n-\tu32 cr1;\n-\tu32 cr2;\n-\tu32 cr3;\n-\tu32 brr;\n-\tu32 gtpr;\n-\tu32 rtor;\n-\tu32 rqr;\n-\tu32 sr;\n-\tu32 icr;\n-\tu32 rd_dr;\n-\tu32 tx_dr;\n+#define CR1_OFFSET(x)\t(x ? 0x0c : 0x00)\n+#define CR3_OFFSET(x)\t(x ? 0x14 : 0x08)\n+#define BRR_OFFSET(x)\t(x ? 0x08 : 0x0c)\n+#define ISR_OFFSET(x)\t(x ? 0x00 : 0x1c)\n+/*\n+ * STM32F4 has one Data Register (DR) for received or transmitted\n+ * data, so map Receive Data Register (RDR) and Transmit Data\n+ * Register (TDR) at the same offset\n+ */\n+#define RDR_OFFSET(x)\t(x ? 0x04 : 0x24)\n+#define TDR_OFFSET(x)\t(x ? 0x04 : 0x28)\n+\n+struct stm32_uart_info {\n+\tu8 uart_enable_bit;\t/* UART_CR1_UE */\n+\tbool stm32f4;\t\t/* true for STM32F4, false otherwise */\n+\tbool has_overrun_disable;\n+};\n+\n+struct stm32_uart_info stm32x7_info = {\n+\t.uart_enable_bit = 0,\n+\t.stm32f4 = false,\n+\t.has_overrun_disable = true,\n };\n \n /* Information about a serial port */\n struct stm32x7_serial_platdata {\n-\tstruct stm32_usart *base; /* address of registers in physical memory */\n+\tfdt_addr_t base; /* address of registers in physical memory */\n+\tstruct stm32_uart_info *uart_info;\n \tunsigned long int clock_rate;\n };\n \n #define USART_CR1_OVER8\t\t\tBIT(15)\n #define USART_CR1_TE\t\t\tBIT(3)\n #define USART_CR1_RE\t\t\tBIT(2)\n-#define USART_CR1_UE\t\t\tBIT(0)\n \n #define USART_CR3_OVRDIS\t\tBIT(12)\n \n", "prefixes": [ "U-Boot", "v1", "3/6" ] }