[{"id":1777366,"web_url":"http://patchwork.ozlabs.org/comment/1777366/","msgid":"<12493a75-76ce-bc6e-6bd4-52ef9dcf4066@gmail.com>","list_archive_url":null,"date":"2017-09-29T06:24:22","subject":"Re: [U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to\n\tSTM32F4 support","submitter":{"id":13793,"url":"http://patchwork.ozlabs.org/api/people/13793/","name":"Bo Shen","email":"voice.shen@gmail.com"},"content":"Hi Patrice,\n For this patch, overall I think you can use more generic method like \ndefine the parameter called ip_version in stm32_uart_info structure, and \naccording to this information to covert base to different register map \nas following, then we can get rid of \"stm32f4\" in stm32_uart_info \nstructure, and easy to extend if you have more versions.\n\n--->8---\n struct stm32_usart_v1 { }; (version 1 register map)\n struct stm32_usart_v2 { }; (version 2 register map)\n\n switch (ip_version) {\n case v1:\n struct stm32_usart_v1 *ptr = (struct stm32_usart_v1 *)base;\n break;\n case v2:\n struct stm32_usart_v1 *ptr = (struct stm32_usart_v1 *)base;\n break;\n }\n---8<---\n\nBest Regards,\nBo Shen\n\nOn 09/27/2017 06:44 AM, patrice.chotard@st.com wrote:\n> From: Patrice Chotard \n> \n> STM32F4 serial IP is similar to F7 and H7, but registers\n> are not located at the same offset and some feature are\n> only supported by F7 and H7 version.\n> \n> Registers offset must be added for each version and also\n> some flags indicated the supported feature.\n> \n> Update registers name to match with datasheet (sr to isr,\n> rx_dr to rdr and tx_dr to tdr) and remove unused regs\n> (cr2, gtpr, rtor, and rqr).\n> \n> Signed-off-by: Patrice Chotard \n> ---\n> drivers/serial/serial_stm32x7.c | 72 ++++++++++++++++++++++++-----------------\n> drivers/serial/serial_stm32x7.h | 38 ++++++++++++++--------\n> 2 files changed, 66 insertions(+), 44 deletions(-)\n> \n> diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c\n> index bafcc36..81a2308 100644\n> --- a/drivers/serial/serial_stm32x7.c\n> +++ b/drivers/serial/serial_stm32x7.c\n> @@ -17,67 +17,79 @@ DECLARE_GLOBAL_DATA_PTR;\n> \n> static int stm32_serial_setbrg(struct udevice *dev, int baudrate)\n> {\n> -\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n> -\tstruct stm32_usart *const usart = plat->base;\n> +\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n> +\tbool stm32f4 = plat->uart_info->stm32f4;\n> +\tfdt_addr_t base = plat->base;\n> \tu32 int_div, mantissa, fraction, oversampling;\n> \n> \tint_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);\n> \n> \tif (int_div < 16) {\n> \t\toversampling = 8;\n> -\t\tsetbits_le32(&usart->cr1, USART_CR1_OVER8);\n> +\t\tsetbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);\n> \t} else {\n> \t\toversampling = 16;\n> -\t\tclrbits_le32(&usart->cr1, USART_CR1_OVER8);\n> +\t\tclrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);\n> \t}\n> \n> \tmantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;\n> \tfraction = int_div % oversampling;\n> \n> -\twritel(mantissa | fraction, &usart->brr);\n> +\twritel(mantissa | fraction, base + BRR_OFFSET(stm32f4));\n> \n> \treturn 0;\n> }\n> \n> static int stm32_serial_getc(struct udevice *dev)\n> {\n> -\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n> -\tstruct stm32_usart *const usart = plat->base;\n> +\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n> +\tbool stm32f4 = plat->uart_info->stm32f4;\n> +\tfdt_addr_t base = plat->base;\n> \n> -\tif ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)\n> +\tif ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)\n> \t\treturn -EAGAIN;\n> \n> -\treturn readl(&usart->rd_dr);\n> +\treturn readl(base + RDR_OFFSET(stm32f4));\n> }\n> \n> static int stm32_serial_putc(struct udevice *dev, const char c)\n> {\n> -\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n> -\tstruct stm32_usart *const usart = plat->base;\n> +\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n> +\tbool stm32f4 = plat->uart_info->stm32f4;\n> +\tfdt_addr_t base = plat->base;\n> \n> -\tif ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)\n> +\tif ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)\n> \t\treturn -EAGAIN;\n> \n> -\twritel(c, &usart->tx_dr);\n> +\twritel(c, base + TDR_OFFSET(stm32f4));\n> \n> \treturn 0;\n> }\n> \n> static int stm32_serial_pending(struct udevice *dev, bool input)\n> {\n> -\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n> -\tstruct stm32_usart *const usart = plat->base;\n> +\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n> +\tbool stm32f4 = plat->uart_info->stm32f4;\n> +\tfdt_addr_t base = plat->base;\n> \n> \tif (input)\n> -\t\treturn readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;\n> +\t\treturn readl(base + ISR_OFFSET(stm32f4)) &\n> +\t\t\tUSART_SR_FLAG_RXNE ? 1 : 0;\n> \telse\n> -\t\treturn readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;\n> +\t\treturn readl(base + ISR_OFFSET(stm32f4)) &\n> +\t\t\tUSART_SR_FLAG_TXE ? 0 : 1;\n> }\n> \n> static int stm32_serial_probe(struct udevice *dev)\n> {\n> -\tstruct stm32x7_serial_platdata *plat = dev->platdata;\n> -\tstruct stm32_usart *const usart = plat->base;\n> +\tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n> +\tfdt_addr_t base = plat->base;\n> +\tbool stm32f4;\n> +\tu8 uart_enable_bit;\n> +\n> +\tplat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);\n> +\tstm32f4 = plat->uart_info->stm32f4;\n> +\tuart_enable_bit = plat->uart_info->uart_enable_bit;\n> \n> #ifdef CONFIG_CLK\n> \tint ret;\n> @@ -100,32 +112,32 @@ static int stm32_serial_probe(struct udevice *dev)\n> \t\treturn plat->clock_rate;\n> \t};\n> \n> -\t/* Disable usart-> disable overrun-> enable usart */\n> -\tclrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);\n> -\tsetbits_le32(&usart->cr3, USART_CR3_OVRDIS);\n> -\tsetbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);\n> +\t/* Disable uart-> disable overrun-> enable uart */\n> +\tclrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |\n> +\t\t BIT(uart_enable_bit));\n> +\tif (plat->uart_info->has_overrun_disable)\n> +\t\tsetbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);\n> +\tsetbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |\n> +\t\t BIT(uart_enable_bit));\n> \n> \treturn 0;\n> }\n> \n> #if CONFIG_IS_ENABLED(OF_CONTROL)\n> static const struct udevice_id stm32_serial_id[] = {\n> -\t{.compatible = \"st,stm32f7-uart\"},\n> -\t{.compatible = \"st,stm32h7-uart\"},\n> +\t{ .compatible = \"st,stm32f7-uart\", .data = (ulong)&stm32x7_info},\n> +\t{ .compatible = \"st,stm32h7-uart\", .data = (ulong)&stm32x7_info},\n> \t{}\n> };\n> \n> static int stm32_serial_ofdata_to_platdata(struct udevice *dev)\n> {\n> \tstruct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\n> -\tfdt_addr_t addr;\n> \n> -\taddr = devfdt_get_addr(dev);\n> -\tif (addr == FDT_ADDR_T_NONE)\n> +\tplat->base = devfdt_get_addr(dev);\n> +\tif (plat->base == FDT_ADDR_T_NONE)\n> \t\treturn -EINVAL;\n> \n> -\tplat->base = (struct stm32_usart *)addr;\n> -\n> \treturn 0;\n> }\n> #endif\n> diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h\n> index 6d36b74..4c6b7d4 100644\n> --- a/drivers/serial/serial_stm32x7.h\n> +++ b/drivers/serial/serial_stm32x7.h\n> @@ -8,30 +8,40 @@\n> #ifndef _SERIAL_STM32_X7_\n> #define _SERIAL_STM32_X7_\n> \n> -struct stm32_usart {\n> -\tu32 cr1;\n> -\tu32 cr2;\n> -\tu32 cr3;\n> -\tu32 brr;\n> -\tu32 gtpr;\n> -\tu32 rtor;\n> -\tu32 rqr;\n> -\tu32 sr;\n> -\tu32 icr;\n> -\tu32 rd_dr;\n> -\tu32 tx_dr;\n> +#define CR1_OFFSET(x)\t(x ? 0x0c : 0x00)\n> +#define CR3_OFFSET(x)\t(x ? 0x14 : 0x08)\n> +#define BRR_OFFSET(x)\t(x ? 0x08 : 0x0c)\n> +#define ISR_OFFSET(x)\t(x ? 0x00 : 0x1c)\n> +/*\n> + * STM32F4 has one Data Register (DR) for received or transmitted\n> + * data, so map Receive Data Register (RDR) and Transmit Data\n> + * Register (TDR) at the same offset\n> + */\n> +#define RDR_OFFSET(x)\t(x ? 0x04 : 0x24)\n> +#define TDR_OFFSET(x)\t(x ? 0x04 : 0x28)\n> +\n> +struct stm32_uart_info {\n> +\tu8 uart_enable_bit;\t/* UART_CR1_UE */\n> +\tbool stm32f4;\t\t/* true for STM32F4, false otherwise */\n> +\tbool has_overrun_disable;\n> +};\n> +\n> +struct stm32_uart_info stm32x7_info = {\n> +\t.uart_enable_bit = 0,\n> +\t.stm32f4 = false,\n> +\t.has_overrun_disable = true,\n> };\n> \n> /* Information about a serial port */\n> struct stm32x7_serial_platdata {\n> -\tstruct stm32_usart *base; /* address of registers in physical memory */\n> +\tfdt_addr_t base; /* address of registers in physical memory */\n> +\tstruct stm32_uart_info *uart_info;\n> \tunsigned long int clock_rate;\n> };\n> \n> #define USART_CR1_OVER8\t\t\tBIT(15)\n> #define USART_CR1_TE\t\t\tBIT(3)\n> #define USART_CR1_RE\t\t\tBIT(2)\n> -#define USART_CR1_UE\t\t\tBIT(0)\n> \n> #define USART_CR3_OVRDIS\t\tBIT(12)\n> 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albert.u.boot@aribaud.net, \n\tsjg@chromium.org, vikas.manocha@st.com","References":"<1506519893-16509-1-git-send-email-patrice.chotard@st.com>\n\t<1506519893-16509-4-git-send-email-patrice.chotard@st.com>","From":"Bo Shen ","Message-ID":"<12493a75-76ce-bc6e-6bd4-52ef9dcf4066@gmail.com>","Date":"Thu, 28 Sep 2017 23:24:22 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506519893-16509-4-git-send-email-patrice.chotard@st.com>","Content-Language":"en-US","Subject":"Re: [U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to\n\tSTM32F4 support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777504,"web_url":"http://patchwork.ozlabs.org/comment/1777504/","msgid":"","list_archive_url":null,"date":"2017-09-29T11:45:38","subject":"Re: [U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to\n\tSTM32F4 support","submitter":{"id":63958,"url":"http://patchwork.ozlabs.org/api/people/63958/","name":"Patrice CHOTARD","email":"patrice.chotard@st.com"},"content":"Hi Bo\r\n\r\nOn 09/29/2017 08:24 AM, Bo Shen wrote:\r\n> Hi Patrice,\r\n>   For this patch, overall I think you can use more generic method like \r\n> define the parameter called ip_version in stm32_uart_info structure, and \r\n> according to this information to covert base to different register map \r\n> as following, then we can get rid of \"stm32f4\" in stm32_uart_info \r\n> structure, and easy to extend if you have more versions.\r\n> \r\n> --->8---\r\n>   struct stm32_usart_v1 { }; (version 1 register map)\r\n>   struct stm32_usart_v2 { }; (version 2 register map)\r\n> \r\n>   switch (ip_version) {\r\n>   case v1:\r\n>     struct stm32_usart_v1 *ptr = (struct stm32_usart_v1 *)base;\r\n>     break;\r\n>   case v2:\r\n>     struct stm32_usart_v1 *ptr = (struct stm32_usart_v1 *)base;\r\n>     break;\r\n>   }\r\n> ---8<---\r\n\r\nIt's another way to solve this problem, i will check if it's more \r\nefficient regarding code/data size\r\n\r\nThanks for the tips.\r\n\r\nPatrice\r\n\r\n> \r\n> Best Regards,\r\n> Bo Shen\r\n> \r\n> On 09/27/2017 06:44 AM, patrice.chotard@st.com wrote:\r\n>> From: Patrice Chotard \r\n>>\r\n>> STM32F4 serial IP is similar to F7 and H7, but registers\r\n>> are not located at the same offset and some feature are\r\n>> only supported by F7 and H7 version.\r\n>>\r\n>> Registers offset must be added for each version and also\r\n>> some flags indicated the supported feature.\r\n>>\r\n>> Update registers name to match with datasheet (sr to isr,\r\n>> rx_dr to rdr and tx_dr to tdr) and remove unused regs\r\n>> (cr2, gtpr, rtor, and rqr).\r\n>>\r\n>> Signed-off-by: Patrice Chotard \r\n>> ---\r\n>>   drivers/serial/serial_stm32x7.c | 72 \r\n>> ++++++++++++++++++++++++-----------------\r\n>>   drivers/serial/serial_stm32x7.h | 38 ++++++++++++++--------\r\n>>   2 files changed, 66 insertions(+), 44 deletions(-)\r\n>>\r\n>> diff --git a/drivers/serial/serial_stm32x7.c \r\n>> b/drivers/serial/serial_stm32x7.c\r\n>> index bafcc36..81a2308 100644\r\n>> --- a/drivers/serial/serial_stm32x7.c\r\n>> +++ b/drivers/serial/serial_stm32x7.c\r\n>> @@ -17,67 +17,79 @@ DECLARE_GLOBAL_DATA_PTR;\r\n>>   static int stm32_serial_setbrg(struct udevice *dev, int baudrate)\r\n>>   {\r\n>> -    struct stm32x7_serial_platdata *plat = dev->platdata;\r\n>> -    struct stm32_usart *const usart = plat->base;\r\n>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\r\n>> +    bool stm32f4 = plat->uart_info->stm32f4;\r\n>> +    fdt_addr_t base = plat->base;\r\n>>       u32 int_div, mantissa, fraction, oversampling;\r\n>>       int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);\r\n>>       if (int_div < 16) {\r\n>>           oversampling = 8;\r\n>> -        setbits_le32(&usart->cr1, USART_CR1_OVER8);\r\n>> +        setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);\r\n>>       } else {\r\n>>           oversampling = 16;\r\n>> -        clrbits_le32(&usart->cr1, USART_CR1_OVER8);\r\n>> +        clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);\r\n>>       }\r\n>>       mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;\r\n>>       fraction = int_div % oversampling;\r\n>> -    writel(mantissa | fraction, &usart->brr);\r\n>> +    writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));\r\n>>       return 0;\r\n>>   }\r\n>>   static int stm32_serial_getc(struct udevice *dev)\r\n>>   {\r\n>> -    struct stm32x7_serial_platdata *plat = dev->platdata;\r\n>> -    struct stm32_usart *const usart = plat->base;\r\n>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\r\n>> +    bool stm32f4 = plat->uart_info->stm32f4;\r\n>> +    fdt_addr_t base = plat->base;\r\n>> -    if ((readl(&usart->sr) & USART_SR_FLAG_RXNE) == 0)\r\n>> +    if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)\r\n>>           return -EAGAIN;\r\n>> -    return readl(&usart->rd_dr);\r\n>> +    return readl(base + RDR_OFFSET(stm32f4));\r\n>>   }\r\n>>   static int stm32_serial_putc(struct udevice *dev, const char c)\r\n>>   {\r\n>> -    struct stm32x7_serial_platdata *plat = dev->platdata;\r\n>> -    struct stm32_usart *const usart = plat->base;\r\n>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\r\n>> +    bool stm32f4 = plat->uart_info->stm32f4;\r\n>> +    fdt_addr_t base = plat->base;\r\n>> -    if ((readl(&usart->sr) & USART_SR_FLAG_TXE) == 0)\r\n>> +    if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)\r\n>>           return -EAGAIN;\r\n>> -    writel(c, &usart->tx_dr);\r\n>> +    writel(c, base + TDR_OFFSET(stm32f4));\r\n>>       return 0;\r\n>>   }\r\n>>   static int stm32_serial_pending(struct udevice *dev, bool input)\r\n>>   {\r\n>> -    struct stm32x7_serial_platdata *plat = dev->platdata;\r\n>> -    struct stm32_usart *const usart = plat->base;\r\n>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\r\n>> +    bool stm32f4 = plat->uart_info->stm32f4;\r\n>> +    fdt_addr_t base = plat->base;\r\n>>       if (input)\r\n>> -        return readl(&usart->sr) & USART_SR_FLAG_RXNE ? 1 : 0;\r\n>> +        return readl(base + ISR_OFFSET(stm32f4)) &\r\n>> +            USART_SR_FLAG_RXNE ? 1 : 0;\r\n>>       else\r\n>> -        return readl(&usart->sr) & USART_SR_FLAG_TXE ? 0 : 1;\r\n>> +        return readl(base + ISR_OFFSET(stm32f4)) &\r\n>> +            USART_SR_FLAG_TXE ? 0 : 1;\r\n>>   }\r\n>>   static int stm32_serial_probe(struct udevice *dev)\r\n>>   {\r\n>> -    struct stm32x7_serial_platdata *plat = dev->platdata;\r\n>> -    struct stm32_usart *const usart = plat->base;\r\n>> +    struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\r\n>> +    fdt_addr_t base = plat->base;\r\n>> +    bool stm32f4;\r\n>> +    u8 uart_enable_bit;\r\n>> +\r\n>> +    plat->uart_info = (struct stm32_uart_info \r\n>> *)dev_get_driver_data(dev);\r\n>> +    stm32f4 = plat->uart_info->stm32f4;\r\n>> +    uart_enable_bit = plat->uart_info->uart_enable_bit;\r\n>>   #ifdef CONFIG_CLK\r\n>>       int ret;\r\n>> @@ -100,32 +112,32 @@ static int stm32_serial_probe(struct udevice *dev)\r\n>>           return plat->clock_rate;\r\n>>       };\r\n>> -    /* Disable usart-> disable overrun-> enable usart */\r\n>> -    clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | \r\n>> USART_CR1_UE);\r\n>> -    setbits_le32(&usart->cr3, USART_CR3_OVRDIS);\r\n>> -    setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | \r\n>> USART_CR1_UE);\r\n>> +    /* Disable uart-> disable overrun-> enable uart */\r\n>> +    clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | \r\n>> USART_CR1_TE |\r\n>> +             BIT(uart_enable_bit));\r\n>> +    if (plat->uart_info->has_overrun_disable)\r\n>> +        setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);\r\n>> +    setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | \r\n>> USART_CR1_TE |\r\n>> +             BIT(uart_enable_bit));\r\n>>       return 0;\r\n>>   }\r\n>>   #if CONFIG_IS_ENABLED(OF_CONTROL)\r\n>>   static const struct udevice_id stm32_serial_id[] = {\r\n>> -    {.compatible = \"st,stm32f7-uart\"},\r\n>> -    {.compatible = \"st,stm32h7-uart\"},\r\n>> +    { .compatible = \"st,stm32f7-uart\", .data = (ulong)&stm32x7_info},\r\n>> +    { .compatible = \"st,stm32h7-uart\", .data = (ulong)&stm32x7_info},\r\n>>       {}\r\n>>   };\r\n>>   static int stm32_serial_ofdata_to_platdata(struct udevice *dev)\r\n>>   {\r\n>>       struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);\r\n>> -    fdt_addr_t addr;\r\n>> -    addr = devfdt_get_addr(dev);\r\n>> -    if (addr == FDT_ADDR_T_NONE)\r\n>> +    plat->base = devfdt_get_addr(dev);\r\n>> +    if (plat->base == FDT_ADDR_T_NONE)\r\n>>           return -EINVAL;\r\n>> -    plat->base = (struct stm32_usart *)addr;\r\n>> -\r\n>>       return 0;\r\n>>   }\r\n>>   #endif\r\n>> diff --git a/drivers/serial/serial_stm32x7.h \r\n>> b/drivers/serial/serial_stm32x7.h\r\n>> index 6d36b74..4c6b7d4 100644\r\n>> --- a/drivers/serial/serial_stm32x7.h\r\n>> +++ b/drivers/serial/serial_stm32x7.h\r\n>> @@ -8,30 +8,40 @@\r\n>>   #ifndef _SERIAL_STM32_X7_\r\n>>   #define _SERIAL_STM32_X7_\r\n>> -struct stm32_usart {\r\n>> -    u32 cr1;\r\n>> -    u32 cr2;\r\n>> -    u32 cr3;\r\n>> -    u32 brr;\r\n>> -    u32 gtpr;\r\n>> -    u32 rtor;\r\n>> -    u32 rqr;\r\n>> -    u32 sr;\r\n>> -    u32 icr;\r\n>> -    u32 rd_dr;\r\n>> -    u32 tx_dr;\r\n>> +#define CR1_OFFSET(x)    (x ? 0x0c : 0x00)\r\n>> +#define CR3_OFFSET(x)    (x ? 0x14 : 0x08)\r\n>> +#define BRR_OFFSET(x)    (x ? 0x08 : 0x0c)\r\n>> +#define ISR_OFFSET(x)    (x ? 0x00 : 0x1c)\r\n>> +/*\r\n>> + * STM32F4 has one Data Register (DR) for received or transmitted\r\n>> + * data, so map Receive Data Register (RDR) and Transmit Data\r\n>> + * Register (TDR) at the same offset\r\n>> + */\r\n>> +#define RDR_OFFSET(x)    (x ? 0x04 : 0x24)\r\n>> +#define TDR_OFFSET(x)    (x ? 0x04 : 0x28)\r\n>> +\r\n>> +struct stm32_uart_info {\r\n>> +    u8 uart_enable_bit;    /* UART_CR1_UE */\r\n>> +    bool stm32f4;        /* true for STM32F4, false otherwise */\r\n>> +    bool has_overrun_disable;\r\n>> +};\r\n>> +\r\n>> +struct stm32_uart_info stm32x7_info = {\r\n>> +    .uart_enable_bit = 0,\r\n>> +    .stm32f4 = false,\r\n>> +    .has_overrun_disable = true,\r\n>>   };\r\n>>   /* Information about a serial port */\r\n>>   struct stm32x7_serial_platdata {\r\n>> -    struct stm32_usart *base;  /* address of registers in physical \r\n>> memory */\r\n>> +    fdt_addr_t base;  /* address of registers in physical memory */\r\n>> +    struct stm32_uart_info *uart_info;\r\n>>       unsigned long int clock_rate;\r\n>>   };\r\n>>   #define USART_CR1_OVER8            BIT(15)\r\n>>   #define USART_CR1_TE            BIT(3)\r\n>>   #define USART_CR1_RE            BIT(2)\r\n>> -#define USART_CR1_UE            BIT(0)\r\n>>   #define USART_CR3_OVRDIS        BIT(12)\r\n>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y3VBH3yrDz9t2h\n\tfor ;\n\tFri, 29 Sep 2017 21:45:59 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 50237C21DCA; Fri, 29 Sep 2017 11:45:52 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby 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[10.75.127.19])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7E80B2618;\n\tFri, 29 Sep 2017 11:45:38 +0000 (GMT)","from SFHDAG6NODE3.st.com (10.75.127.18) by SFHDAG7NODE1.st.com\n\t(10.75.127.19) with Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tFri, 29 Sep 2017 13:45:38 +0200","from SFHDAG6NODE3.st.com ([fe80::d04:5337:ab17:b6f6]) by\n\tSFHDAG6NODE3.st.com ([fe80::d04:5337:ab17:b6f6%20]) with mapi id\n\t15.00.1178.000; Fri, 29 Sep 2017 13:45:38 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","From":"Patrice CHOTARD ","To":"Bo Shen , \"u-boot@lists.denx.de\"\n\t, \"albert.u.boot@aribaud.net\"\n\t, \"sjg@chromium.org\" ,\n\t\"Vikas MANOCHA\" ","Thread-Topic":"[U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to\n\tSTM32F4 support","Thread-Index":"AQHTN5bRhRflblDnx0+d2Qka/2/wPaLLRngAgABZwoA=","Date":"Fri, 29 Sep 2017 11:45:38 +0000","Message-ID":"","References":"<1506519893-16509-1-git-send-email-patrice.chotard@st.com>\n\t<1506519893-16509-4-git-send-email-patrice.chotard@st.com>\n\t<12493a75-76ce-bc6e-6bd4-52ef9dcf4066@gmail.com>","In-Reply-To":"<12493a75-76ce-bc6e-6bd4-52ef9dcf4066@gmail.com>","Accept-Language":"fr-FR, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","user-agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","x-ms-exchange-messagesentrepresentingtype":"1","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[10.75.127.46]","Content-ID":"","MIME-Version":"1.0","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-29_03:, , signatures=0","Subject":"Re: [U-Boot] [PATCH v1 3/6] serial: stm32x7: prepare the ground to\n\tSTM32F4 support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1783016,"web_url":"http://patchwork.ozlabs.org/comment/1783016/","msgid":"<20171009170106.GJ12015@bill-the-cat>","list_archive_url":null,"date":"2017-10-09T17:01:06","subject":"Re: [U-Boot] [U-Boot, v1,\n\t3/6] serial: stm32x7: prepare the ground to STM32F4 support","submitter":{"id":65875,"url":"http://patchwork.ozlabs.org/api/people/65875/","name":"Tom Rini","email":"trini@konsulko.com"},"content":"On Wed, Sep 27, 2017 at 03:44:50PM +0200, patrice.chotard@st.com wrote:\n\n> From: Patrice Chotard \n> \n> STM32F4 serial IP is similar to F7 and H7, but registers\n> are not located at the same offset and some feature are\n> only supported by F7 and H7 version.\n> \n> Registers offset must be added for each version and also\n> some flags indicated the supported feature.\n> \n> Update registers name to match with datasheet (sr to isr,\n> rx_dr to rdr and tx_dr to tdr) and remove unused regs\n> (cr2, gtpr, rtor, and rqr).\n> \n> Signed-off-by: Patrice Chotard \n\nApplied to u-boot/master, thanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=konsulko.com header.i=@konsulko.com\n\theader.b=\"SEmOuc1m\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org 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","To":"patrice.chotard@st.com","Message-ID":"<20171009170106.GJ12015@bill-the-cat>","References":"<1506519893-16509-4-git-send-email-patrice.chotard@st.com>","MIME-Version":"1.0","In-Reply-To":"<1506519893-16509-4-git-send-email-patrice.chotard@st.com>","User-Agent":"Mutt/1.5.24 (2015-08-30)","Cc":"u-boot@lists.denx.de","Subject":"Re: [U-Boot] [U-Boot, v1,\n\t3/6] serial: stm32x7: prepare the ground to STM32F4 support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"multipart/mixed;\n\tboundary=\"===============2692589893126689840==\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]