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GET /api/patches/819159/?format=api
{ "id": 819159, "url": "http://patchwork.ozlabs.org/api/patches/819159/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170927133241.21036-2-shameerali.kolothum.thodi@huawei.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170927133241.21036-2-shameerali.kolothum.thodi@huawei.com>", "list_archive_url": null, "date": "2017-09-27T13:32:37", "name": "[v8,1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "0129236b997cae228e8615dbcc3126a22ff26db7", "submitter": { "id": 70507, "url": "http://patchwork.ozlabs.org/api/people/70507/?format=api", "name": "Shameerali Kolothum Thodi", "email": "shameerali.kolothum.thodi@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170927133241.21036-2-shameerali.kolothum.thodi@huawei.com/mbox/", "series": [ { "id": 5369, "url": "http://patchwork.ozlabs.org/api/series/5369/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=5369", "date": "2017-09-27T13:32:36", "name": "iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/5369/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/819159/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/819159/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2JjC6Wcrz9sPr\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tWed, 27 Sep 2017 23:35:11 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752677AbdI0NfK (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 27 Sep 2017 09:35:10 -0400", "from szxga04-in.huawei.com ([45.249.212.190]:7449 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751959AbdI0NfK (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Wed, 27 Sep 2017 09:35:10 -0400", "from 172.30.72.58 (EHLO DGGEMS401-HUB.china.huawei.com)\n\t([172.30.72.58])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DIB16842; Wed, 27 Sep 2017 21:35:06 +0800 (CST)", "from S00345302A-PC.china.huawei.com (10.203.177.212) by\n\tDGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP\n\tServer id 14.3.301.0; Wed, 27 Sep 2017 21:34:58 +0800" ], "From": "Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>", "To": "<lorenzo.pieralisi@arm.com>, <marc.zyngier@arm.com>,\n\t<sudeep.holla@arm.com>, <will.deacon@arm.com>,\n\t<robin.murphy@arm.com>, <joro@8bytes.org>, <mark.rutland@arm.com>,\n\t<robh@kernel.org>", "CC": "<gabriele.paoloni@huawei.com>, <john.garry@huawei.com>,\n\t<iommu@lists.linux-foundation.org>,\n\t<linux-arm-kernel@lists.infradead.org>, \n\t<linux-acpi@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<devel@acpica.org>, <linuxarm@huawei.com>,\n\t<wangzhou1@hisilicon.com>, <guohanjun@huawei.com>,\n\tShameer Kolothum <shameerali.kolothum.thodi@huawei.com>", "Subject": "[PATCH v8 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon\n\terratum 161010801", "Date": "Wed, 27 Sep 2017 14:32:37 +0100", "Message-ID": "<20170927133241.21036-2-shameerali.kolothum.thodi@huawei.com>", "X-Mailer": "git-send-email 2.12.0.windows.1", "In-Reply-To": "<20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com>", "References": "<20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.203.177.212]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A020206.59CBA90A.015A, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "1199e1a103f72e2595b31297b988f396", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "From: John Garry <john.garry@huawei.com>\n\nThe HiSilicon erratum 161010801 describes the limitation of HiSilicon\nplatforms hip06/hip07 to support the SMMU mappings for MSI transactions.\n\nOn these platforms, GICv3 ITS translator is presented with the deviceID\nby extending the MSI payload data to 64 bits to include the deviceID.\nHence, the PCIe controller on this platforms has to differentiate the MSI\npayload against other DMA payload and has to modify the MSI payload.\nThis basically makes it difficult for this platforms to have a SMMU\ntranslation for MSI.\n\nThis patch adds a compatible string to implement this errata for\nHiSilicon Hi161x SMMUv3 model on hip06/hip07 platforms.\n\nAlso, the arm64 silicon errata is updated with this same erratum.\n\nSigned-off-by: John Garry <john.garry@huawei.com>\n[Shameer: Modified to use compatible string for errata]\nSigned-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>\n---\n Documentation/arm64/silicon-errata.txt | 1 +\n Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 9 ++++++++-\n 2 files changed, 9 insertions(+), 1 deletion(-)", "diff": "diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt\nindex 66e8ce1..02816b1 100644\n--- a/Documentation/arm64/silicon-errata.txt\n+++ b/Documentation/arm64/silicon-errata.txt\n@@ -70,6 +70,7 @@ stable kernels.\n | | | | |\n | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |\n | Hisilicon | Hip0{6,7} | #161010701 | N/A |\n+| Hisilicon | Hip0{6,7} | #161010801 | N/A |\n | | | | |\n | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |\n | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |\ndiff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\nindex c9abbf3..3b0d599 100644\n--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n@@ -7,11 +7,18 @@ the PCIe specification.\n \n ** SMMUv3 required properties:\n \n-- compatible : Should include:\n+- compatible : Should be one of:\n+\n+ \"arm,smmu-v3\"\n+ \"hisilicon,hi161x-smmu-v3\"\n+\n+ depending on the particular implementation.\n \n * \"arm,smmu-v3\" for any SMMUv3 compliant\n implementation. This entry should be last in the\n compatible list.\n+ * \"hisilicon,hi161x-smmu-v3\" for HiSilicon hi161x\n+ SMMUv3 implementation on hip06/hip07 platforms.\n \n - reg : Base address and size of the SMMU.\n \n", "prefixes": [ "v8", "1/5" ] }