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{
    "id": 818390,
    "url": "http://patchwork.ozlabs.org/api/patches/818390/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/b5fd087892544cd17042a4aa9dc0289fb761352c.1506380746.git.digetx@gmail.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
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    },
    "msgid": "<b5fd087892544cd17042a4aa9dc0289fb761352c.1506380746.git.digetx@gmail.com>",
    "list_archive_url": null,
    "date": "2017-09-25T23:22:02",
    "name": "[v1,1/5] clk: tegra: Add AHB DMA clock entry",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "2998a2f46e2c4f3c1f5e82aee876ce6d4870c0e9",
    "submitter": {
        "id": 18124,
        "url": "http://patchwork.ozlabs.org/api/people/18124/?format=api",
        "name": "Dmitry Osipenko",
        "email": "digetx@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/b5fd087892544cd17042a4aa9dc0289fb761352c.1506380746.git.digetx@gmail.com/mbox/",
    "series": [
        {
            "id": 5029,
            "url": "http://patchwork.ozlabs.org/api/series/5029/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=5029",
            "date": "2017-09-25T23:22:01",
            "name": "NVIDIA Tegra AHB DMA controller driver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/5029/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/818390/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/818390/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
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        "X-Received": "by 10.46.65.27 with SMTP id o27mr3466373lja.142.1506381865539;\n\tMon, 25 Sep 2017 16:24:25 -0700 (PDT)",
        "From": "Dmitry Osipenko <digetx@gmail.com>",
        "To": "Thierry Reding <thierry.reding@gmail.com>,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tLaxman Dewangan <ldewangan@nvidia.com>,\n\tPeter De Schrijver <pdeschrijver@nvidia.com>,\n\tPrashant Gaikwad <pgaikwad@nvidia.com>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@codeaurora.org>, Rob Herring <robh+dt@kernel.org>,\n\tVinod Koul <vinod.koul@intel.com>",
        "Cc": "linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,\n\tdmaengine@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org",
        "Subject": "[PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry",
        "Date": "Tue, 26 Sep 2017 02:22:02 +0300",
        "Message-Id": "<b5fd087892544cd17042a4aa9dc0289fb761352c.1506380746.git.digetx@gmail.com>",
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        "In-Reply-To": [
            "<cover.1506380746.git.digetx@gmail.com>",
            "<cover.1506380746.git.digetx@gmail.com>"
        ],
        "References": [
            "<cover.1506380746.git.digetx@gmail.com>",
            "<cover.1506380746.git.digetx@gmail.com>"
        ],
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "AHB DMA presents on Tegra20/30. Add missing entries, so that driver\nfor AHB DMA could be implemented.\n\nSigned-off-by: Dmitry Osipenko <digetx@gmail.com>\n---\n drivers/clk/tegra/clk-id.h           | 1 +\n drivers/clk/tegra/clk-tegra-periph.c | 1 +\n drivers/clk/tegra/clk-tegra20.c      | 6 ++++++\n drivers/clk/tegra/clk-tegra30.c      | 2 ++\n 4 files changed, 10 insertions(+)",
    "diff": "diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h\nindex 689f344377a7..c1661b47bbda 100644\n--- a/drivers/clk/tegra/clk-id.h\n+++ b/drivers/clk/tegra/clk-id.h\n@@ -12,6 +12,7 @@ enum clk_id {\n \ttegra_clk_amx,\n \ttegra_clk_amx1,\n \ttegra_clk_apb2ape,\n+\ttegra_clk_ahbdma,\n \ttegra_clk_apbdma,\n \ttegra_clk_apbif,\n \ttegra_clk_ape,\ndiff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c\nindex 848255cc0209..95a3d8c95f06 100644\n--- a/drivers/clk/tegra/clk-tegra-periph.c\n+++ b/drivers/clk/tegra/clk-tegra-periph.c\n@@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {\n \tGATE(\"timer\", \"clk_m\", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),\n \tGATE(\"isp\", \"clk_m\", 23, 0, tegra_clk_isp, 0),\n \tGATE(\"vcp\", \"clk_m\", 29, 0, tegra_clk_vcp, 0),\n+\tGATE(\"ahbdma\", \"clk_m\", 33, 0, tegra_clk_ahbdma, 0),\n \tGATE(\"apbdma\", \"clk_m\", 34, 0, tegra_clk_apbdma, 0),\n \tGATE(\"kbc\", \"clk_32k\", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),\n \tGATE(\"fuse\", \"clk_m\", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),\ndiff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c\nindex 837e5cbd60e9..e76c0d292ca7 100644\n--- a/drivers/clk/tegra/clk-tegra20.c\n+++ b/drivers/clk/tegra/clk-tegra20.c\n@@ -449,6 +449,7 @@ static struct tegra_devclk devclks[] __initdata = {\n \t{ .con_id = \"audio\", .dt_id = TEGRA20_CLK_AUDIO },\n \t{ .con_id = \"audio_2x\", .dt_id = TEGRA20_CLK_AUDIO_2X },\n \t{ .dev_id = \"tegra20-ac97\", .dt_id = TEGRA20_CLK_AC97 },\n+\t{ .dev_id = \"tegra-ahbdma\", .dt_id = TEGRA20_CLK_AHBDMA },\n \t{ .dev_id = \"tegra-apbdma\", .dt_id = TEGRA20_CLK_APBDMA },\n \t{ .dev_id = \"rtc-tegra\", .dt_id = TEGRA20_CLK_RTC },\n \t{ .dev_id = \"timer\", .dt_id = TEGRA20_CLK_TIMER },\n@@ -806,6 +807,11 @@ static void __init tegra20_periph_clk_init(void)\n \t\t\t\t    clk_base, 0, 3, periph_clk_enb_refcnt);\n \tclks[TEGRA20_CLK_AC97] = clk;\n \n+\t/* ahbdma */\n+\tclk = tegra_clk_register_periph_gate(\"ahbdma\", \"hclk\", 0, clk_base,\n+\t\t\t\t    0, 33, periph_clk_enb_refcnt);\n+\tclks[TEGRA20_CLK_AHBDMA] = clk;\n+\n \t/* apbdma */\n \tclk = tegra_clk_register_periph_gate(\"apbdma\", \"pclk\", 0, clk_base,\n \t\t\t\t    0, 34, periph_clk_enb_refcnt);\ndiff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c\nindex a2d163f759b4..e99701557f29 100644\n--- a/drivers/clk/tegra/clk-tegra30.c\n+++ b/drivers/clk/tegra/clk-tegra30.c\n@@ -612,6 +612,7 @@ static struct tegra_devclk devclks[] __initdata = {\n \t{ .con_id = \"fuse_burn\", .dev_id = \"fuse-tegra\", .dt_id = TEGRA30_CLK_FUSE_BURN },\n \t{ .con_id = \"apbif\", .dev_id = \"tegra30-ahub\", .dt_id = TEGRA30_CLK_APBIF },\n \t{ .con_id = \"hda2hdmi\", .dev_id = \"tegra30-hda\", .dt_id = TEGRA30_CLK_HDA2HDMI },\n+\t{ .dev_id = \"tegra-ahbdma\", .dt_id = TEGRA30_CLK_AHBDMA },\n \t{ .dev_id = \"tegra-apbdma\", .dt_id = TEGRA30_CLK_APBDMA },\n \t{ .dev_id = \"rtc-tegra\", .dt_id = TEGRA30_CLK_RTC },\n \t{ .dev_id = \"timer\", .dt_id = TEGRA30_CLK_TIMER },\n@@ -788,6 +789,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {\n \t[tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },\n \t[tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },\n \t[tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },\n+\t[tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },\n \t[tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },\n \t[tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },\n \t[tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },\n",
    "prefixes": [
        "v1",
        "1/5"
    ]
}