[{"id":1775316,"web_url":"http://patchwork.ozlabs.org/comment/1775316/","msgid":"<20170926095611.GW6290@tbergstrom-lnx.Nvidia.com>","list_archive_url":null,"date":"2017-09-26T09:56:11","subject":"Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry","submitter":{"id":9849,"url":"http://patchwork.ozlabs.org/api/people/9849/","name":"Peter De Schrijver","email":"pdeschrijver@nvidia.com"},"content":"On Tue, Sep 26, 2017 at 02:22:02AM +0300, Dmitry Osipenko wrote:\n> AHB DMA presents on Tegra20/30. Add missing entries, so that driver\n> for AHB DMA could be implemented.\n> \n> Signed-off-by: Dmitry Osipenko \n> ---\n> drivers/clk/tegra/clk-id.h | 1 +\n> drivers/clk/tegra/clk-tegra-periph.c | 1 +\n> drivers/clk/tegra/clk-tegra20.c | 6 ++++++\n> drivers/clk/tegra/clk-tegra30.c | 2 ++\n> 4 files changed, 10 insertions(+)\n> \n> diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h\n> index 689f344377a7..c1661b47bbda 100644\n> --- a/drivers/clk/tegra/clk-id.h\n> +++ b/drivers/clk/tegra/clk-id.h\n> @@ -12,6 +12,7 @@ enum clk_id {\n> \ttegra_clk_amx,\n> \ttegra_clk_amx1,\n> \ttegra_clk_apb2ape,\n> +\ttegra_clk_ahbdma,\n> \ttegra_clk_apbdma,\n> \ttegra_clk_apbif,\n> \ttegra_clk_ape,\n> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c\n> index 848255cc0209..95a3d8c95f06 100644\n> --- a/drivers/clk/tegra/clk-tegra-periph.c\n> +++ b/drivers/clk/tegra/clk-tegra-periph.c\n> @@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {\n> \tGATE(\"timer\", \"clk_m\", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),\n> \tGATE(\"isp\", \"clk_m\", 23, 0, tegra_clk_isp, 0),\n> \tGATE(\"vcp\", \"clk_m\", 29, 0, tegra_clk_vcp, 0),\n> +\tGATE(\"ahbdma\", \"clk_m\", 33, 0, tegra_clk_ahbdma, 0),\n\nParent for this should be hclk on Tegra30 and later chips as well..\n\n> \tGATE(\"apbdma\", \"clk_m\", 34, 0, tegra_clk_apbdma, 0),\n> \tGATE(\"kbc\", \"clk_32k\", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),\n> \tGATE(\"fuse\", \"clk_m\", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),\n> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c\n> index 837e5cbd60e9..e76c0d292ca7 100644\n> --- a/drivers/clk/tegra/clk-tegra20.c\n> +++ b/drivers/clk/tegra/clk-tegra20.c\n> @@ -449,6 +449,7 @@ static struct tegra_devclk devclks[] __initdata = {\n> \t{ .con_id = \"audio\", .dt_id = TEGRA20_CLK_AUDIO },\n> \t{ .con_id = \"audio_2x\", .dt_id = TEGRA20_CLK_AUDIO_2X },\n> \t{ .dev_id = \"tegra20-ac97\", .dt_id = TEGRA20_CLK_AC97 },\n> +\t{ .dev_id = \"tegra-ahbdma\", .dt_id = TEGRA20_CLK_AHBDMA },\n\nThis isn't needed if you use DT bindings to get the clock handle.\n\n> \t{ .dev_id = \"tegra-apbdma\", .dt_id = TEGRA20_CLK_APBDMA },\n> \t{ .dev_id = \"rtc-tegra\", .dt_id = TEGRA20_CLK_RTC },\n> \t{ .dev_id = \"timer\", .dt_id = TEGRA20_CLK_TIMER },\n> @@ -806,6 +807,11 @@ static void __init tegra20_periph_clk_init(void)\n> \t\t\t\t clk_base, 0, 3, periph_clk_enb_refcnt);\n> \tclks[TEGRA20_CLK_AC97] = clk;\n> \n> +\t/* ahbdma */\n> +\tclk = tegra_clk_register_periph_gate(\"ahbdma\", \"hclk\", 0, clk_base,\n> +\t\t\t\t 0, 33, periph_clk_enb_refcnt);\n> +\tclks[TEGRA20_CLK_AHBDMA] = clk;\n> +\n\nYou can use the generic definition here if you correct the entry above.\n\n> \t/* apbdma */\n> \tclk = tegra_clk_register_periph_gate(\"apbdma\", \"pclk\", 0, clk_base,\n> \t\t\t\t 0, 34, periph_clk_enb_refcnt);\n> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c\n> index a2d163f759b4..e99701557f29 100644\n> --- a/drivers/clk/tegra/clk-tegra30.c\n> +++ b/drivers/clk/tegra/clk-tegra30.c\n> @@ -612,6 +612,7 @@ static struct tegra_devclk devclks[] __initdata = {\n> \t{ .con_id = \"fuse_burn\", .dev_id = \"fuse-tegra\", .dt_id = TEGRA30_CLK_FUSE_BURN },\n> \t{ .con_id = \"apbif\", .dev_id = \"tegra30-ahub\", .dt_id = TEGRA30_CLK_APBIF },\n> \t{ .con_id = \"hda2hdmi\", .dev_id = \"tegra30-hda\", .dt_id = TEGRA30_CLK_HDA2HDMI },\n> +\t{ .dev_id = \"tegra-ahbdma\", .dt_id = TEGRA30_CLK_AHBDMA },\n\nSame as for Tegra20.\n\n> \t{ .dev_id = \"tegra-apbdma\", .dt_id = TEGRA30_CLK_APBDMA },\n> \t{ .dev_id = \"rtc-tegra\", .dt_id = TEGRA30_CLK_RTC },\n> \t{ .dev_id = \"timer\", .dt_id = TEGRA30_CLK_TIMER },\n> @@ -788,6 +789,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {\n> \t[tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },\n> \t[tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },\n> \t[tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },\n> +\t[tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },\n> \t[tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },\n> \t[tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },\n> \t[tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },\n\nCheers,\n\nPeter.\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-tegra\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1bwx2b2rz9tXc\n\tfor ;\n\tTue, 26 Sep 2017 19:57:53 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1030257AbdIZJ52 (ORCPT );\n\tTue, 26 Sep 2017 05:57:28 -0400","from hqemgate15.nvidia.com ([216.228.121.64]:9694 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S934183AbdIZJ50 (ORCPT\n\t);\n\tTue, 26 Sep 2017 05:57:26 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com\n\tid ; Tue, 26 Sep 2017 02:56:53 -0700","from HQMAIL105.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 26 Sep 2017 02:56:55 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL105.nvidia.com\n\t(172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tTue, 26 Sep 2017 09:56:14 +0000","from tbergstrom-lnx.Nvidia.com (10.21.24.170) by\n\tUKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS)\n\tid 15.0.1293.2; Tue, 26 Sep 2017 09:56:11 +0000","by tbergstrom-lnx.Nvidia.com (Postfix, from userid 1002)\n\tid 120DAF805F4; Tue, 26 Sep 2017 12:56:11 +0300 (EEST)"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 26 Sep 2017 02:56:55 -0700","Date":"Tue, 26 Sep 2017 12:56:11 +0300","From":"Peter De Schrijver ","To":"Dmitry Osipenko ","CC":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\t\"Prashant Gaikwad\" ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\t\"Vinod Koul\" , ,\n\t, ,\n\t, ","Subject":"Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry","Message-ID":"<20170926095611.GW6290@tbergstrom-lnx.Nvidia.com>","References":"\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Disposition":"inline","In-Reply-To":"","X-NVConfidentiality":"public","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-Originating-IP":"[10.21.24.170]","X-ClientProxiedBy":"UKMAIL101.nvidia.com (10.26.138.13) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}},{"id":1775594,"web_url":"http://patchwork.ozlabs.org/comment/1775594/","msgid":"","list_archive_url":null,"date":"2017-09-26T14:46:01","subject":"Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 26.09.2017 12:56, Peter De Schrijver wrote:\n> On Tue, Sep 26, 2017 at 02:22:02AM +0300, Dmitry Osipenko wrote:\n>> AHB DMA presents on Tegra20/30. Add missing entries, so that driver\n>> for AHB DMA could be implemented.\n>>\n>> Signed-off-by: Dmitry Osipenko \n>> ---\n>> drivers/clk/tegra/clk-id.h | 1 +\n>> drivers/clk/tegra/clk-tegra-periph.c | 1 +\n>> drivers/clk/tegra/clk-tegra20.c | 6 ++++++\n>> drivers/clk/tegra/clk-tegra30.c | 2 ++\n>> 4 files changed, 10 insertions(+)\n>>\n>> diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h\n>> index 689f344377a7..c1661b47bbda 100644\n>> --- a/drivers/clk/tegra/clk-id.h\n>> +++ b/drivers/clk/tegra/clk-id.h\n>> @@ -12,6 +12,7 @@ enum clk_id {\n>> \ttegra_clk_amx,\n>> \ttegra_clk_amx1,\n>> \ttegra_clk_apb2ape,\n>> +\ttegra_clk_ahbdma,\n>> \ttegra_clk_apbdma,\n>> \ttegra_clk_apbif,\n>> \ttegra_clk_ape,\n>> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c\n>> index 848255cc0209..95a3d8c95f06 100644\n>> --- a/drivers/clk/tegra/clk-tegra-periph.c\n>> +++ b/drivers/clk/tegra/clk-tegra-periph.c\n>> @@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {\n>> \tGATE(\"timer\", \"clk_m\", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),\n>> \tGATE(\"isp\", \"clk_m\", 23, 0, tegra_clk_isp, 0),\n>> \tGATE(\"vcp\", \"clk_m\", 29, 0, tegra_clk_vcp, 0),\n>> +\tGATE(\"ahbdma\", \"clk_m\", 33, 0, tegra_clk_ahbdma, 0),\n> \n> Parent for this should be hclk on Tegra30 and later chips as well..\n> \n\nIt looks like other clocks have a wrong parent too here, aren't they? Like for\nexample \"apbdma\" should have \"pclk\" as a parent, isn't it?\n\n>> \tGATE(\"apbdma\", \"clk_m\", 34, 0, tegra_clk_apbdma, 0),\n>> \tGATE(\"kbc\", \"clk_32k\", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),\n>> \tGATE(\"fuse\", \"clk_m\", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),\n>> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c\n>> index 837e5cbd60e9..e76c0d292ca7 100644\n>> --- a/drivers/clk/tegra/clk-tegra20.c\n>> +++ b/drivers/clk/tegra/clk-tegra20.c\n>> @@ -449,6 +449,7 @@ static struct tegra_devclk devclks[] __initdata = {\n>> \t{ .con_id = \"audio\", .dt_id = TEGRA20_CLK_AUDIO },\n>> \t{ .con_id = \"audio_2x\", .dt_id = TEGRA20_CLK_AUDIO_2X },\n>> \t{ .dev_id = \"tegra20-ac97\", .dt_id = TEGRA20_CLK_AC97 },\n>> +\t{ .dev_id = \"tegra-ahbdma\", .dt_id = TEGRA20_CLK_AHBDMA },\n> \n> This isn't needed if you use DT bindings to get the clock handle.\n> \n\nYes, I added it for consistency. Shouldn't we get rid of that all legacy stuff\nalready?\n\n>> \t{ .dev_id = \"tegra-apbdma\", .dt_id = TEGRA20_CLK_APBDMA },\n>> \t{ .dev_id = \"rtc-tegra\", .dt_id = TEGRA20_CLK_RTC },\n>> \t{ .dev_id = \"timer\", .dt_id = TEGRA20_CLK_TIMER },\n>> @@ -806,6 +807,11 @@ static void __init tegra20_periph_clk_init(void)\n>> \t\t\t\t clk_base, 0, 3, periph_clk_enb_refcnt);\n>> \tclks[TEGRA20_CLK_AC97] = clk;\n>> \n>> +\t/* ahbdma */\n>> +\tclk = tegra_clk_register_periph_gate(\"ahbdma\", \"hclk\", 0, clk_base,\n>> +\t\t\t\t 0, 33, periph_clk_enb_refcnt);\n>> +\tclks[TEGRA20_CLK_AHBDMA] = clk;\n>> +\n> \n> You can use the generic definition here if you correct the entry above.\n> \n\nGood point, same applies to \"apbdma\". Thank you for the suggestion.\n\n>> \t/* apbdma */\n>> \tclk = tegra_clk_register_periph_gate(\"apbdma\", \"pclk\", 0, clk_base,\n>> \t\t\t\t 0, 34, periph_clk_enb_refcnt);\n>> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c\n>> index a2d163f759b4..e99701557f29 100644\n>> --- a/drivers/clk/tegra/clk-tegra30.c\n>> +++ b/drivers/clk/tegra/clk-tegra30.c\n>> @@ -612,6 +612,7 @@ static struct tegra_devclk devclks[] __initdata = {\n>> \t{ .con_id = \"fuse_burn\", .dev_id = \"fuse-tegra\", .dt_id = TEGRA30_CLK_FUSE_BURN },\n>> \t{ .con_id = \"apbif\", .dev_id = \"tegra30-ahub\", .dt_id = TEGRA30_CLK_APBIF },\n>> \t{ .con_id = \"hda2hdmi\", .dev_id = \"tegra30-hda\", .dt_id = TEGRA30_CLK_HDA2HDMI },\n>> +\t{ .dev_id = \"tegra-ahbdma\", .dt_id = TEGRA30_CLK_AHBDMA },\n> \n> Same as for Tegra20.\n> \n>> \t{ .dev_id = \"tegra-apbdma\", .dt_id = TEGRA30_CLK_APBDMA },\n>> \t{ .dev_id = \"rtc-tegra\", .dt_id = TEGRA30_CLK_RTC },\n>> \t{ .dev_id = \"timer\", .dt_id = TEGRA30_CLK_TIMER },\n>> @@ -788,6 +789,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {\n>> \t[tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },\n>> \t[tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },\n>> \t[tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },\n>> +\t[tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },\n>> \t[tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },\n>> \t[tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },\n>> \t[tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },\n> \n> Cheers,\n> \n> Peter.\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170926095611.GW6290@tbergstrom-lnx.Nvidia.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}},{"id":1776126,"web_url":"http://patchwork.ozlabs.org/comment/1776126/","msgid":"<20170927083605.GA6290@tbergstrom-lnx.Nvidia.com>","list_archive_url":null,"date":"2017-09-27T08:36:05","subject":"Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry","submitter":{"id":9849,"url":"http://patchwork.ozlabs.org/api/people/9849/","name":"Peter De Schrijver","email":"pdeschrijver@nvidia.com"},"content":"On Tue, Sep 26, 2017 at 05:46:01PM +0300, Dmitry Osipenko wrote:\n> On 26.09.2017 12:56, Peter De Schrijver wrote:\n> > On Tue, Sep 26, 2017 at 02:22:02AM +0300, Dmitry Osipenko wrote:\n> >> AHB DMA presents on Tegra20/30. Add missing entries, so that driver\n> >> for AHB DMA could be implemented.\n> >>\n> >> Signed-off-by: Dmitry Osipenko \n> >> ---\n> >> drivers/clk/tegra/clk-id.h | 1 +\n> >> drivers/clk/tegra/clk-tegra-periph.c | 1 +\n> >> drivers/clk/tegra/clk-tegra20.c | 6 ++++++\n> >> drivers/clk/tegra/clk-tegra30.c | 2 ++\n> >> 4 files changed, 10 insertions(+)\n> >>\n> >> diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h\n> >> index 689f344377a7..c1661b47bbda 100644\n> >> --- a/drivers/clk/tegra/clk-id.h\n> >> +++ b/drivers/clk/tegra/clk-id.h\n> >> @@ -12,6 +12,7 @@ enum clk_id {\n> >> \ttegra_clk_amx,\n> >> \ttegra_clk_amx1,\n> >> \ttegra_clk_apb2ape,\n> >> +\ttegra_clk_ahbdma,\n> >> \ttegra_clk_apbdma,\n> >> \ttegra_clk_apbif,\n> >> \ttegra_clk_ape,\n> >> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c\n> >> index 848255cc0209..95a3d8c95f06 100644\n> >> --- a/drivers/clk/tegra/clk-tegra-periph.c\n> >> +++ b/drivers/clk/tegra/clk-tegra-periph.c\n> >> @@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {\n> >> \tGATE(\"timer\", \"clk_m\", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),\n> >> \tGATE(\"isp\", \"clk_m\", 23, 0, tegra_clk_isp, 0),\n> >> \tGATE(\"vcp\", \"clk_m\", 29, 0, tegra_clk_vcp, 0),\n> >> +\tGATE(\"ahbdma\", \"clk_m\", 33, 0, tegra_clk_ahbdma, 0),\n> > \n> > Parent for this should be hclk on Tegra30 and later chips as well..\n> > \n> \n> It looks like other clocks have a wrong parent too here, aren't they? Like for\n> example \"apbdma\" should have \"pclk\" as a parent, isn't it?\n> \n\nYes. That is correct.\n\n> >> \tGATE(\"apbdma\", \"clk_m\", 34, 0, tegra_clk_apbdma, 0),\n> >> \tGATE(\"kbc\", \"clk_32k\", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),\n> >> \tGATE(\"fuse\", \"clk_m\", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),\n> >> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c\n> >> index 837e5cbd60e9..e76c0d292ca7 100644\n> >> --- a/drivers/clk/tegra/clk-tegra20.c\n> >> +++ b/drivers/clk/tegra/clk-tegra20.c\n> >> @@ -449,6 +449,7 @@ static struct tegra_devclk devclks[] __initdata = {\n> >> \t{ .con_id = \"audio\", .dt_id = TEGRA20_CLK_AUDIO },\n> >> \t{ .con_id = \"audio_2x\", .dt_id = TEGRA20_CLK_AUDIO_2X },\n> >> \t{ .dev_id = \"tegra20-ac97\", .dt_id = TEGRA20_CLK_AC97 },\n> >> +\t{ .dev_id = \"tegra-ahbdma\", .dt_id = TEGRA20_CLK_AHBDMA },\n> > \n> > This isn't needed if you use DT bindings to get the clock handle.\n> > \n> \n> Yes, I added it for consistency. Shouldn't we get rid of that all legacy stuff\n> already?\n> \n\nWe probably should, but we can start by not adding more :)\n\n> >> \t{ .dev_id = \"tegra-apbdma\", .dt_id = TEGRA20_CLK_APBDMA },\n> >> \t{ .dev_id = \"rtc-tegra\", .dt_id = TEGRA20_CLK_RTC },\n> >> \t{ .dev_id = \"timer\", .dt_id = TEGRA20_CLK_TIMER },\n> >> @@ -806,6 +807,11 @@ static void __init tegra20_periph_clk_init(void)\n> >> \t\t\t\t clk_base, 0, 3, periph_clk_enb_refcnt);\n> >> \tclks[TEGRA20_CLK_AC97] = clk;\n> >> \n> >> +\t/* ahbdma */\n> >> +\tclk = tegra_clk_register_periph_gate(\"ahbdma\", \"hclk\", 0, clk_base,\n> >> +\t\t\t\t 0, 33, periph_clk_enb_refcnt);\n> >> +\tclks[TEGRA20_CLK_AHBDMA] = clk;\n> >> +\n> > \n> > You can use the generic definition here if you correct the entry above.\n> > \n> \n> Good point, same applies to \"apbdma\". Thank you for the suggestion.\n> \n\nIndeed.\n\nPeter.\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-tegra\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2B5W4BSnz9t4Z\n\tfor ;\n\tWed, 27 Sep 2017 18:37:19 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752395AbdI0Ig7 (ORCPT );\n\tWed, 27 Sep 2017 04:36:59 -0400","from hqemgate16.nvidia.com ([216.228.121.65]:12962 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751830AbdI0Ig4 (ORCPT\n\t);\n\tWed, 27 Sep 2017 04:36:56 -0400","from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com\n\tid ; Wed, 27 Sep 2017 01:36:23 -0700","from HQMAIL106.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tWed, 27 Sep 2017 01:36:24 -0700","from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL106.nvidia.com\n\t(172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 27 Sep 2017 08:36:10 +0000","from tbergstrom-lnx.Nvidia.com (10.21.24.170) by\n\tUKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS)\n\tid 15.0.1293.2; Wed, 27 Sep 2017 08:36:06 +0000","by tbergstrom-lnx.Nvidia.com (Postfix, from userid 1002)\n\tid 5B2BDF8002C; Wed, 27 Sep 2017 11:36:05 +0300 (EEST)"],"X-PGP-Universal":"processed;\n\tby hqpgpgate102.nvidia.com on Wed, 27 Sep 2017 01:36:24 -0700","Date":"Wed, 27 Sep 2017 11:36:05 +0300","From":"Peter De Schrijver ","To":"Dmitry Osipenko ","CC":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\t\"Prashant Gaikwad\" ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\t\"Vinod Koul\" , ,\n\t, ,\n\t, ","Subject":"Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry","Message-ID":"<20170927083605.GA6290@tbergstrom-lnx.Nvidia.com>","References":"\n\t\n\t<20170926095611.GW6290@tbergstrom-lnx.Nvidia.com>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Disposition":"inline","In-Reply-To":"","X-NVConfidentiality":"public","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-Originating-IP":"[10.21.24.170]","X-ClientProxiedBy":"UKMAIL101.nvidia.com (10.26.138.13) To\n\tUKMAIL101.nvidia.com (10.26.138.13)","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}},{"id":1776189,"web_url":"http://patchwork.ozlabs.org/comment/1776189/","msgid":"<168d1f44-21ae-86c5-7d9b-981c370d012b@gmail.com>","list_archive_url":null,"date":"2017-09-27T09:41:55","subject":"Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 27.09.2017 11:36, Peter De Schrijver wrote:\n> On Tue, Sep 26, 2017 at 05:46:01PM +0300, Dmitry Osipenko wrote:\n>> On 26.09.2017 12:56, Peter De Schrijver wrote:\n>>> On Tue, Sep 26, 2017 at 02:22:02AM +0300, Dmitry Osipenko wrote:\n>>>> AHB DMA presents on Tegra20/30. Add missing entries, so that driver\n>>>> for AHB DMA could be implemented.\n>>>>\n>>>> Signed-off-by: Dmitry Osipenko \n>>>> ---\n>>>> drivers/clk/tegra/clk-id.h | 1 +\n>>>> drivers/clk/tegra/clk-tegra-periph.c | 1 +\n>>>> drivers/clk/tegra/clk-tegra20.c | 6 ++++++\n>>>> drivers/clk/tegra/clk-tegra30.c | 2 ++\n>>>> 4 files changed, 10 insertions(+)\n>>>>\n>>>> diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h\n>>>> index 689f344377a7..c1661b47bbda 100644\n>>>> --- a/drivers/clk/tegra/clk-id.h\n>>>> +++ b/drivers/clk/tegra/clk-id.h\n>>>> @@ -12,6 +12,7 @@ enum clk_id {\n>>>> \ttegra_clk_amx,\n>>>> \ttegra_clk_amx1,\n>>>> \ttegra_clk_apb2ape,\n>>>> +\ttegra_clk_ahbdma,\n>>>> \ttegra_clk_apbdma,\n>>>> \ttegra_clk_apbif,\n>>>> \ttegra_clk_ape,\n>>>> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c\n>>>> index 848255cc0209..95a3d8c95f06 100644\n>>>> --- a/drivers/clk/tegra/clk-tegra-periph.c\n>>>> +++ b/drivers/clk/tegra/clk-tegra-periph.c\n>>>> @@ -823,6 +823,7 @@ static struct tegra_periph_init_data gate_clks[] = {\n>>>> \tGATE(\"timer\", \"clk_m\", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),\n>>>> \tGATE(\"isp\", \"clk_m\", 23, 0, tegra_clk_isp, 0),\n>>>> \tGATE(\"vcp\", \"clk_m\", 29, 0, tegra_clk_vcp, 0),\n>>>> +\tGATE(\"ahbdma\", \"clk_m\", 33, 0, tegra_clk_ahbdma, 0),\n>>>\n>>> Parent for this should be hclk on Tegra30 and later chips as well..\n>>>\n>>\n>> It looks like other clocks have a wrong parent too here, aren't they? Like for\n>> example \"apbdma\" should have \"pclk\" as a parent, isn't it?\n>>\n> \n> Yes. That is correct.\n> \n\nOkay, I'll fix it in V2.\n\n>>>> \tGATE(\"apbdma\", \"clk_m\", 34, 0, tegra_clk_apbdma, 0),\n>>>> \tGATE(\"kbc\", \"clk_32k\", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),\n>>>> \tGATE(\"fuse\", \"clk_m\", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),\n>>>> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c\n>>>> index 837e5cbd60e9..e76c0d292ca7 100644\n>>>> --- a/drivers/clk/tegra/clk-tegra20.c\n>>>> +++ b/drivers/clk/tegra/clk-tegra20.c\n>>>> @@ -449,6 +449,7 @@ static struct tegra_devclk devclks[] __initdata = {\n>>>> \t{ .con_id = \"audio\", .dt_id = TEGRA20_CLK_AUDIO },\n>>>> \t{ .con_id = \"audio_2x\", .dt_id = TEGRA20_CLK_AUDIO_2X },\n>>>> \t{ .dev_id = \"tegra20-ac97\", .dt_id = TEGRA20_CLK_AC97 },\n>>>> +\t{ .dev_id = \"tegra-ahbdma\", .dt_id = TEGRA20_CLK_AHBDMA },\n>>>\n>>> This isn't needed if you use DT bindings to get the clock handle.\n>>>\n>>\n>> Yes, I added it for consistency. Shouldn't we get rid of that all legacy stuff\n>> already?\n>>\n> \n> We probably should, but we can start by not adding more :)\n> \n\nSure ;)\n\n>>>> \t{ .dev_id = \"tegra-apbdma\", .dt_id = TEGRA20_CLK_APBDMA },\n>>>> \t{ .dev_id = \"rtc-tegra\", .dt_id = TEGRA20_CLK_RTC },\n>>>> \t{ .dev_id = \"timer\", .dt_id = TEGRA20_CLK_TIMER },\n>>>> @@ -806,6 +807,11 @@ static void __init tegra20_periph_clk_init(void)\n>>>> \t\t\t\t clk_base, 0, 3, periph_clk_enb_refcnt);\n>>>> \tclks[TEGRA20_CLK_AC97] = clk;\n>>>> \n>>>> +\t/* ahbdma */\n>>>> +\tclk = tegra_clk_register_periph_gate(\"ahbdma\", \"hclk\", 0, clk_base,\n>>>> +\t\t\t\t 0, 33, periph_clk_enb_refcnt);\n>>>> +\tclks[TEGRA20_CLK_AHBDMA] = clk;\n>>>> +\n>>>\n>>> You can use the generic definition here if you correct the entry above.\n>>>\n>>\n>> Good point, same applies to \"apbdma\". Thank you for the suggestion.\n>>\n> \n> Indeed.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"W0B41KWX\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2CXr11Ncz9tXp\n\tfor ;\n\tWed, 27 Sep 2017 19:42:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752310AbdI0JmD (ORCPT );\n\tWed, 27 Sep 2017 05:42:03 -0400","from mail-wr0-f194.google.com ([209.85.128.194]:34663 \"EHLO\n\tmail-wr0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752016AbdI0JmA (ORCPT\n\t);\n\tWed, 27 Sep 2017 05:42:00 -0400","by mail-wr0-f194.google.com with SMTP id z1so1187421wre.1;\n\tWed, 27 Sep 2017 02:41:59 -0700 (PDT)","from [192.168.1.145] (ppp109-252-90-109.pppoe.spdop.ru.\n\t[109.252.90.109]) by smtp.googlemail.com with ESMTPSA id\n\tl187sm1666697lfg.25.2017.09.27.02.41.56\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 27 Sep 2017 02:41:57 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=KYrxVeF4Rgwq40ctSgFlHnPb0UGvlwG5GdLYSCZRMPQ=;\n\tb=W0B41KWXlZuXqKWjTmBDhx27C3eFq+DKxbz3iK5gpMXlvttDz6G9uckeot4GDtYJta\n\t/QuezrggB7qUgLY8m0P+V8t7GiGxdV12/tGf+XJdmTqT2EAiyMJu0AYe4US7eOPHxMNH\n\tOn1unGBE0snOExpSvDBSJ3gFxDVGHLYiKQyBWFJUFyv8WSaD3DzD3w05I7lXL+SL0TLj\n\t1X/aPxPCW29nnHEAJUR8tIqYf2rqFr3hDzfulzbWzGfVl8xkfgHUMh0klF19JWw+lk9Z\n\t9dNNqespGhIB44508EqwCaoExA6jkFZz470H2DbUo8f+DP1zpzfNpYbDR0QpzZqkr714\n\tMDUw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=KYrxVeF4Rgwq40ctSgFlHnPb0UGvlwG5GdLYSCZRMPQ=;\n\tb=kG/B7FizjYww9F2mK8+XaH1VzyxBehlqrL2Yv3srTz+XzKlTgytzdsZ5iOPB45lGPo\n\tY0W1jCJkwbSuS/Ens8MH/PZVxmYrlx1WzMntpkj2S/ii2rEUt4S0bhEjuEXQlvhJ57cy\n\tvTD4NlDcOD07JOzX/qAMIY0Okocvkd1hDyTC4of+8OQCW9iKpDbTH/KbYo2RjLuatWRS\n\tB1mjv8+a+h+5P7C2UJ3xxhh+kn72t1QMUPGC4K3IEi7TL1Bz2m6LZuOPduuOgv5YLsGw\n\tT3eCrT4BpyTdNrzafRpf4uiyK3z0SvYmKF5sgiDjOhBXtjWBPXq2xRZ351cZ+e6A4bm8\n\t1jCQ==","X-Gm-Message-State":"AMCzsaWwJZNZkbi4uUamksTOlunveqwiUnN3fYoij6FKoyqFRpSRZ5d0\n\tQuE6T1CkPrxm9DPTjJ7EvQ+wBn8y","X-Google-Smtp-Source":"AOwi7QBneR8PzP/Nex23d4DK386Xa9Gwe1LBVjLM62CFCgtsHXA9QDG0u6gKA0+Di01i0M5rJuA9VA==","X-Received":"by 10.25.150.3 with SMTP id y3mr339522lfd.237.1506505318320;\n\tWed, 27 Sep 2017 02:41:58 -0700 (PDT)","Subject":"Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry","To":"Peter De Schrijver ","Cc":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd , Rob Herring ,\n\tVinod Koul , linux-tegra@vger.kernel.org,\n\tdevicetree@vger.kernel.org, dmaengine@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org","References":"\n\t\n\t<20170926095611.GW6290@tbergstrom-lnx.Nvidia.com>\n\t\n\t<20170927083605.GA6290@tbergstrom-lnx.Nvidia.com>","From":"Dmitry Osipenko ","Message-ID":"<168d1f44-21ae-86c5-7d9b-981c370d012b@gmail.com>","Date":"Wed, 27 Sep 2017 12:41:55 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170927083605.GA6290@tbergstrom-lnx.Nvidia.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}}]