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GET /api/patches/818120/?format=api
{ "id": 818120, "url": "http://patchwork.ozlabs.org/api/patches/818120/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-17-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506328815-23733-17-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-09-25T08:40:12", "name": "[U-Boot,v2,16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "1ec5e67edda973e7b1d9e9996ba01817d90a3417", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-17-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 4901, "url": "http://patchwork.ozlabs.org/api/series/4901/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4901", "date": "2017-09-25T08:39:56", "name": "Add FPGA, SDRAM, SPL loads U-boot & booting to console", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/4901/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/818120/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/818120/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0ydr3sWJz9s76\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 25 Sep 2017 18:57:36 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 07A9EC2200D; Mon, 25 Sep 2017 08:43:54 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id CF87AC21DCA;\n\tMon, 25 Sep 2017 08:41:25 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 3FCF1C21FDD; Mon, 25 Sep 2017 08:41:02 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 7D1E6C22039\n\tfor <u-boot@lists.denx.de>; Mon, 25 Sep 2017 08:40:58 +0000 (UTC)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Sep 2017 01:40:58 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.95])\n\tby fmsmga005.fm.intel.com with ESMTP; 25 Sep 2017 01:40:56 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080199\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Mon, 25 Sep 2017 16:40:12 +0800", "Message-Id": "<1506328815-23733-17-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>", "References": "<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nEnhance preloader header with both additional program length and program\nentry offset attributes, which offset is relative to the start of program\nheader.\n\nSigned-off-by: Tien Fong Chee <tien.fong.chee@intel.com>\n---\n arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--\n 1 file changed, 9 insertions(+), 2 deletions(-)", "diff": "diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h\nindex 22d9e7f..33c9368 100644\n--- a/arch/arm/mach-socfpga/include/mach/boot0.h\n+++ b/arch/arm/mach-socfpga/include/mach/boot0.h\n@@ -11,8 +11,15 @@\n \t.balignl 64,0xf33db33f;\n \n \t.word\t0x1337c0d3;\t/* SoCFPGA preloader validation word */\n-\t.word\t0xc01df00d;\t/* Version, flags, length */\n-\t.word\t0xcafec0d3;\t/* Checksum, zero-pad */\n+\t.word\t0xc01df00d; /* Header length(2B),flags(1B),version(1B) */\n+#ifndef CONFIG_TARGET_SOCFPGA_GEN5\n+\t.word\t0xfeedface; /* Program length(4B) */\n+\t.word\t0xf00dcafe; /*\n+\t\t\t * Program entry offset(4B),relative to\n+\t\t\t * the start of program header\n+\t\t\t */\n+#endif\n+\t.word\t0xcafec0d3;\t/* Simple checksum(2B),spare offset(2B) */\n \tnop;\n \n \tb reset;\t\t/* SoCFPGA jumps here */\n", "prefixes": [ "U-Boot", "v2", "16/19" ] }