[{"id":1774610,"web_url":"http://patchwork.ozlabs.org/comment/1774610/","msgid":"<74b5459c-f4c4-7457-d041-1a12833e23a8@denx.de>","list_archive_url":null,"date":"2017-09-25T09:23:01","subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> Enhance preloader header with both additional program length and program\n> entry offset attributes, which offset is relative to the start of program\n> header.\n> \n> Signed-off-by: Tien Fong Chee \n> ---\n> arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--\n> 1 file changed, 9 insertions(+), 2 deletions(-)\n> \n> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h\n> index 22d9e7f..33c9368 100644\n> --- a/arch/arm/mach-socfpga/include/mach/boot0.h\n> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h\n> @@ -11,8 +11,15 @@\n> \t.balignl 64,0xf33db33f;\n> \n> \t.word\t0x1337c0d3;\t/* SoCFPGA preloader validation word */\n> -\t.word\t0xc01df00d;\t/* Version, flags, length */\n> -\t.word\t0xcafec0d3;\t/* Checksum, zero-pad */\n> +\t.word\t0xc01df00d; /* Header length(2B),flags(1B),version(1B) */\n> +#ifndef CONFIG_TARGET_SOCFPGA_GEN5\n> +\t.word\t0xfeedface; /* Program length(4B) */\n\nKeep this indent intact, then it won't generate these crappy - entries.\n\n> +\t.word\t0xf00dcafe; /*\n> +\t\t\t * Program entry offset(4B),relative to\n> +\t\t\t * the start of program header\n> +\t\t\t */\n> +#endif\n> +\t.word\t0xcafec0d3;\t/* Simple checksum(2B),spare offset(2B) */\n> \tnop;\n> \n> \tb reset;\t\t/* SoCFPGA jumps here */\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y10F71Z3gz9tX3\n\tfor ;\n\tMon, 25 Sep 2017 20:09:47 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid E111BC2218A; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-17-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Ching Liang See ,\n\tWestergteen Dalon ,\n\tTien Fong ","Subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775147,"web_url":"http://patchwork.ozlabs.org/comment/1775147/","msgid":"<1506400929.27760.7.camel@intel.com>","list_archive_url":null,"date":"2017-09-26T04:42:10","subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\r\n> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > \r\n> > From: Tien Fong Chee \r\n> > \r\n> > Enhance preloader header with both additional program length and\r\n> > program\r\n> > entry offset attributes, which offset is relative to the start of\r\n> > program\r\n> > header.\r\n> > \r\n> > Signed-off-by: Tien Fong Chee \r\n> > ---\r\n> >  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--\r\n> >  1 file changed, 9 insertions(+), 2 deletions(-)\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > b/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > index 22d9e7f..33c9368 100644\r\n> > --- a/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > @@ -11,8 +11,15 @@\r\n> >  \t.balignl 64,0xf33db33f;\r\n> >  \r\n> >  \t.word\t0x1337c0d3;\t/* SoCFPGA preloader\r\n> > validation word */\r\n> > -\t.word\t0xc01df00d;\t/* Version, flags, length\r\n> > */\r\n> > -\t.word\t0xcafec0d3;\t/* Checksum, zero-pad */\r\n> > +\t.word\t0xc01df00d; /* Header\r\n> > length(2B),flags(1B),version(1B) */\r\n> > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5\r\n> > +\t.word\t0xfeedface; /* Program length(4B) */\r\n> Keep this indent intact, then it won't generate these crappy -\r\n> entries.\r\n> \r\nAre you saying to keep the comment indent intact, and allign with 1st\r\ncomment  /* SoCFPGA preloader validation word */ ?\r\n> > \r\n> > +\t.word\t0xf00dcafe; /*\r\n> > +\t\t\t     * Program entry offset(4B),relative\r\n> > to\r\n> > +\t\t\t     * the start of program header\r\n> > +\t\t\t     */\r\n> > +#endif\r\n> > +\t.word\t0xcafec0d3;\t/* Simple\r\n> > checksum(2B),spare offset(2B) */\r\n> >  \tnop;\r\n> >  \r\n> >  \tb reset;\t\t/* SoCFPGA jumps here */\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1Swv4rMJz9t49\n\tfor ;\n\tTue, 26 Sep 2017 14:42:23 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 64100C21D8B; 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d=\"scan'208\";a=\"139425015\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program\n\theader to support Arria 10","Thread-Index":"AQHTNdoGK+JGo6DL10GHT3W7PhsTTaLEzfOAgAFD3IA=","Date":"Tue, 26 Sep 2017 04:42:10 +0000","Message-ID":"<1506400929.27760.7.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-17-git-send-email-tien.fong.chee@intel.com>\n\t<74b5459c-f4c4-7457-d041-1a12833e23a8@denx.de>","In-Reply-To":"<74b5459c-f4c4-7457-d041-1a12833e23a8@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"<569C8BE9FF58FD47BA8AB8545DB0BEBA@intel.com>","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775374,"web_url":"http://patchwork.ozlabs.org/comment/1775374/","msgid":"<18dda297-48b7-48ef-612e-d5d3ad906418@denx.de>","list_archive_url":null,"date":"2017-09-26T10:37:58","subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:\n> On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\n>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>\n>>> From: Tien Fong Chee \n>>>\n>>> Enhance preloader header with both additional program length and\n>>> program\n>>> entry offset attributes, which offset is relative to the start of\n>>> program\n>>> header.\n>>>\n>>> Signed-off-by: Tien Fong Chee \n>>> ---\n>>>  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--\n>>>  1 file changed, 9 insertions(+), 2 deletions(-)\n>>>\n>>> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h\n>>> b/arch/arm/mach-socfpga/include/mach/boot0.h\n>>> index 22d9e7f..33c9368 100644\n>>> --- a/arch/arm/mach-socfpga/include/mach/boot0.h\n>>> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h\n>>> @@ -11,8 +11,15 @@\n>>>  \t.balignl 64,0xf33db33f;\n>>>  \n>>>  \t.word\t0x1337c0d3;\t/* SoCFPGA preloader\n>>> validation word */\n>>> -\t.word\t0xc01df00d;\t/* Version, flags, length\n>>> */\n>>> -\t.word\t0xcafec0d3;\t/* Checksum, zero-pad */\n>>> +\t.word\t0xc01df00d; /* Header\n>>> length(2B),flags(1B),version(1B) */\n>>> +#ifndef CONFIG_TARGET_SOCFPGA_GEN5\n>>> +\t.word\t0xfeedface; /* Program length(4B) */\n>> Keep this indent intact, then it won't generate these crappy -\n>> entries.\n>>\n> Are you saying to keep the comment indent intact, and allign with 1st\n> comment  /* SoCFPGA preloader validation word */ ?\n\nJust look at the diff and make sure that it only changes the relevant\nparts, not extras due to indent changes.\n\n>>>\n>>> +\t.word\t0xf00dcafe; /*\n>>> +\t\t\t     * Program entry offset(4B),relative\n>>> to\n>>> +\t\t\t     * the start of program header\n>>> +\t\t\t     */\n>>> +#endif\n>>> +\t.word\t0xcafec0d3;\t/* Simple\n>>> checksum(2B),spare offset(2B) */\n>>>  \tnop;\n>>>  \n>>>  \tb reset;\t\t/* SoCFPGA jumps here */\n>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Tue, 26 Sep 2017 13:07:38 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tTue, 26 Sep 2017 13:07:38 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"jcYbknkGsexSwYoAfSYO8ofCJxuV97UcgQGKK69yLA0=","To":"\"Chee, Tien Fong\" ,\n\t\"u-boot@lists.denx.de\" ","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-17-git-send-email-tien.fong.chee@intel.com>\n\t<74b5459c-f4c4-7457-d041-1a12833e23a8@denx.de>\n\t<1506400929.27760.7.camel@intel.com>","From":"Marek Vasut ","Message-ID":"<18dda297-48b7-48ef-612e-d5d3ad906418@denx.de>","Date":"Tue, 26 Sep 2017 12:37:58 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506400929.27760.7.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776011,"web_url":"http://patchwork.ozlabs.org/comment/1776011/","msgid":"<1506483003.3589.10.camel@intel.com>","list_archive_url":null,"date":"2017-09-27T03:30:04","subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:\r\n> On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > \r\n> > > > \r\n> > > > From: Tien Fong Chee \r\n> > > > \r\n> > > > Enhance preloader header with both additional program length\r\n> > > > and\r\n> > > > program\r\n> > > > entry offset attributes, which offset is relative to the start\r\n> > > > of\r\n> > > > program\r\n> > > > header.\r\n> > > > \r\n> > > > Signed-off-by: Tien Fong Chee \r\n> > > > ---\r\n> > > >  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--\r\n> > > >  1 file changed, 9 insertions(+), 2 deletions(-)\r\n> > > > \r\n> > > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > > > b/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > > > index 22d9e7f..33c9368 100644\r\n> > > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > > > @@ -11,8 +11,15 @@\r\n> > > >  \t.balignl 64,0xf33db33f;\r\n> > > >  \r\n> > > >  \t.word\t0x1337c0d3;\t/* SoCFPGA preloader\r\n> > > > validation word */\r\n> > > > -\t.word\t0xc01df00d;\t/* Version, flags,\r\n> > > > length\r\n> > > > */\r\n> > > > -\t.word\t0xcafec0d3;\t/* Checksum, zero-pad\r\n> > > > */\r\n> > > > +\t.word\t0xc01df00d; /* Header\r\n> > > > length(2B),flags(1B),version(1B) */\r\n> > > > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5\r\n> > > > +\t.word\t0xfeedface; /* Program length(4B) */\r\n> > > Keep this indent intact, then it won't generate these crappy -\r\n> > > entries.\r\n> > > \r\n> > Are you saying to keep the comment indent intact, and allign with\r\n> > 1st\r\n> > comment  /* SoCFPGA preloader validation word */ ?\r\n> Just look at the diff and make sure that it only changes the relevant\r\n> parts, not extras due to indent changes.\r\n> \r\nNot get you, which particular change is due to indent changes only?\r\nSome changes are for re-writing more descriptive comment. And some new\r\nadding header attributes to support Arria 10.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > +\t.word\t0xf00dcafe; /*\r\n> > > > +\t\t\t     * Program entry\r\n> > > > offset(4B),relative\r\n> > > > to\r\n> > > > +\t\t\t     * the start of program header\r\n> > > > +\t\t\t     */\r\n> > > > +#endif\r\n> > > > +\t.word\t0xcafec0d3;\t/* Simple\r\n> > > > checksum(2B),spare offset(2B) */\r\n> > > >  \tnop;\r\n> > > >  \r\n> > > >  \tb reset;\t\t/* SoCFPGA jumps here */\r\n> > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y23HL3158z9t4Z\n\tfor ;\n\tWed, 27 Sep 2017 13:30:22 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 20431C21C46; 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d=\"scan'208\";a=\"156457758\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program\n\theader to support Arria 10","Thread-Index":"AQHTNdoGK+JGo6DL10GHT3W7PhsTTaLEzfOAgAFD3ICAAGNqAIABGsaA","Date":"Wed, 27 Sep 2017 03:30:04 +0000","Message-ID":"<1506483003.3589.10.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-17-git-send-email-tien.fong.chee@intel.com>\n\t<74b5459c-f4c4-7457-d041-1a12833e23a8@denx.de>\n\t<1506400929.27760.7.camel@intel.com>\n\t<18dda297-48b7-48ef-612e-d5d3ad906418@denx.de>","In-Reply-To":"<18dda297-48b7-48ef-612e-d5d3ad906418@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776187,"web_url":"http://patchwork.ozlabs.org/comment/1776187/","msgid":"<001d44d1-f54f-04e8-0941-728c34ad3e09@denx.de>","list_archive_url":null,"date":"2017-09-27T08:33:59","subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/27/2017 05:30 AM, Chee, Tien Fong wrote:\n> On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:\n>> On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:\n>>>\n>>> On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\n>>>>\n>>>> On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\n>>>>>\n>>>>>\n>>>>> From: Tien Fong Chee \n>>>>>\n>>>>> Enhance preloader header with both additional program length\n>>>>> and\n>>>>> program\n>>>>> entry offset attributes, which offset is relative to the start\n>>>>> of\n>>>>> program\n>>>>> header.\n>>>>>\n>>>>> Signed-off-by: Tien Fong Chee \n>>>>> ---\n>>>>>  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++--\n>>>>>  1 file changed, 9 insertions(+), 2 deletions(-)\n>>>>>\n>>>>> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h\n>>>>> b/arch/arm/mach-socfpga/include/mach/boot0.h\n>>>>> index 22d9e7f..33c9368 100644\n>>>>> --- a/arch/arm/mach-socfpga/include/mach/boot0.h\n>>>>> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h\n>>>>> @@ -11,8 +11,15 @@\n>>>>>  \t.balignl 64,0xf33db33f;\n>>>>>  \n>>>>>  \t.word\t0x1337c0d3;\t/* SoCFPGA preloader\n>>>>> validation word */\n>>>>> -\t.word\t0xc01df00d;\t/* Version, flags,\n>>>>> length\n>>>>> */\n>>>>> -\t.word\t0xcafec0d3;\t/* Checksum, zero-pad\n>>>>> */\n>>>>> +\t.word\t0xc01df00d; /* Header\n>>>>> length(2B),flags(1B),version(1B) */\n>>>>> +#ifndef CONFIG_TARGET_SOCFPGA_GEN5\n>>>>> +\t.word\t0xfeedface; /* Program length(4B) */\n>>>> Keep this indent intact, then it won't generate these crappy -\n>>>> entries.\n>>>>\n>>> Are you saying to keep the comment indent intact, and allign with\n>>> 1st\n>>> comment  /* SoCFPGA preloader validation word */ ?\n>> Just look at the diff and make sure that it only changes the relevant\n>> parts, not extras due to indent changes.\n>>\n> Not get you, which particular change is due to indent changes only?\n> Some changes are for re-writing more descriptive comment. And some new\n> adding header attributes to support Arria 10.\n\nAaargh, then don't do two things in one patch.\n\n>>>\n>>>>\n>>>>>\n>>>>>\n>>>>> +\t.word\t0xf00dcafe; /*\n>>>>> +\t\t\t     * Program entry\n>>>>> offset(4B),relative\n>>>>> to\n>>>>> +\t\t\t     * the start of program header\n>>>>> +\t\t\t     */\n>>>>> +#endif\n>>>>> +\t.word\t0xcafec0d3;\t/* Simple\n>>>>> checksum(2B),spare offset(2B) */\n>>>>>  \tnop;\n>>>>>  \n>>>>>  \tb reset;\t\t/* SoCFPGA jumps here */\n>>>>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2CQF3qn2z9tXT\n\tfor ;\n\tWed, 27 Sep 2017 19:36:53 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 471A2C21E31; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506483003.3589.10.camel@intel.com>","Content-Language":"en-US","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776727,"web_url":"http://patchwork.ozlabs.org/comment/1776727/","msgid":"<1506566791.3589.39.camel@intel.com>","list_archive_url":null,"date":"2017-09-28T02:46:38","subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"content":"On Rab, 2017-09-27 at 10:33 +0200, Marek Vasut wrote:\r\n> On 09/27/2017 05:30 AM, Chee, Tien Fong wrote:\r\n> > \r\n> > On Sel, 2017-09-26 at 12:37 +0200, Marek Vasut wrote:\r\n> > > \r\n> > > On 09/26/2017 06:42 AM, Chee, Tien Fong wrote:\r\n> > > > \r\n> > > > \r\n> > > > On Isn, 2017-09-25 at 11:23 +0200, Marek Vasut wrote:\r\n> > > > > \r\n> > > > > \r\n> > > > > On 09/25/2017 10:40 AM, tien.fong.chee@intel.com wrote:\r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > From: Tien Fong Chee \r\n> > > > > > \r\n> > > > > > Enhance preloader header with both additional program\r\n> > > > > > length\r\n> > > > > > and\r\n> > > > > > program\r\n> > > > > > entry offset attributes, which offset is relative to the\r\n> > > > > > start\r\n> > > > > > of\r\n> > > > > > program\r\n> > > > > > header.\r\n> > > > > > \r\n> > > > > > Signed-off-by: Tien Fong Chee \r\n> > > > > > ---\r\n> > > > > >  arch/arm/mach-socfpga/include/mach/boot0.h | 11 +++++++++-\r\n> > > > > > -\r\n> > > > > >  1 file changed, 9 insertions(+), 2 deletions(-)\r\n> > > > > > \r\n> > > > > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > > > > > b/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > > > > > index 22d9e7f..33c9368 100644\r\n> > > > > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > > > > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h\r\n> > > > > > @@ -11,8 +11,15 @@\r\n> > > > > >  \t.balignl 64,0xf33db33f;\r\n> > > > > >  \r\n> > > > > >  \t.word\t0x1337c0d3;\t/* SoCFPGA\r\n> > > > > > preloader\r\n> > > > > > validation word */\r\n> > > > > > -\t.word\t0xc01df00d;\t/* Version, flags,\r\n> > > > > > length\r\n> > > > > > */\r\n> > > > > > -\t.word\t0xcafec0d3;\t/* Checksum, zero-\r\n> > > > > > pad\r\n> > > > > > */\r\n> > > > > > +\t.word\t0xc01df00d; /* Header\r\n> > > > > > length(2B),flags(1B),version(1B) */\r\n> > > > > > +#ifndef CONFIG_TARGET_SOCFPGA_GEN5\r\n> > > > > > +\t.word\t0xfeedface; /* Program length(4B) */\r\n> > > > > Keep this indent intact, then it won't generate these crappy\r\n> > > > > -\r\n> > > > > entries.\r\n> > > > > \r\n> > > > Are you saying to keep the comment indent intact, and allign\r\n> > > > with\r\n> > > > 1st\r\n> > > > comment  /* SoCFPGA preloader validation word */ ?\r\n> > > Just look at the diff and make sure that it only changes the\r\n> > > relevant\r\n> > > parts, not extras due to indent changes.\r\n> > > \r\n> > Not get you, which particular change is due to indent changes only?\r\n> > Some changes are for re-writing more descriptive comment. And some\r\n> > new\r\n> > adding header attributes to support Arria 10.\r\n> Aaargh, then don't do two things in one patch.\r\n> \r\nI can split them.\r\n> > \r\n> > > \r\n> > > > \r\n> > > > \r\n> > > > > \r\n> > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > \r\n> > > > > > +\t.word\t0xf00dcafe; /*\r\n> > > > > > +\t\t\t     * Program entry\r\n> > > > > > offset(4B),relative\r\n> > > > > > to\r\n> > > > > > +\t\t\t     * the start of program header\r\n> > > > > > +\t\t\t     */\r\n> > > > > > +#endif\r\n> > > > > > +\t.word\t0xcafec0d3;\t/* Simple\r\n> > > > > > checksum(2B),spare offset(2B) */\r\n> > > > > >  \tnop;\r\n> > > > > >  \r\n> > > > > >  \tb reset;\t\t/* SoCFPGA jumps here */\r\n> > > > > > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2fGp1N2Wz9t5C\n\tfor ;\n\tThu, 28 Sep 2017 12:46:56 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid A7723C21CB3; Thu, 28 Sep 2017 02:46:48 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 34A15C21C51;\n\tThu, 28 Sep 2017 02:46:45 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 25B08C21C51; Thu, 28 Sep 2017 02:46:44 +0000 (UTC)","from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby lists.denx.de (Postfix) with ESMTPS id 11B85C21C4A\n\tfor ; Thu, 28 Sep 2017 02:46:42 +0000 (UTC)","from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Sep 2017 19:46:40 -0700","from pgsmsx107.gar.corp.intel.com ([10.221.44.105])\n\tby fmsmga004.fm.intel.com with ESMTP; 27 Sep 2017 19:46:39 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX107.gar.corp.intel.com ([169.254.7.200]) with mapi id\n\t14.03.0319.002; Thu, 28 Sep 2017 10:46:38 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.3 required=5.0 tests=RCVD_IN_DNSWL_MED\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,447,1500966000\"; d=\"scan'208\";a=\"317076439\"","From":"\"Chee, Tien Fong\" ","To":"\"marex@denx.de\" , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program\n\theader to support Arria 10","Thread-Index":"AQHTNdoGK+JGo6DL10GHT3W7PhsTTaLEzfOAgAFD3ICAAGNqAIABGsaAgABU64CAATFAgA==","Date":"Thu, 28 Sep 2017 02:46:38 +0000","Message-ID":"<1506566791.3589.39.camel@intel.com>","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-17-git-send-email-tien.fong.chee@intel.com>\n\t<74b5459c-f4c4-7457-d041-1a12833e23a8@denx.de>\n\t<1506400929.27760.7.camel@intel.com>\n\t<18dda297-48b7-48ef-612e-d5d3ad906418@denx.de>\n\t<1506483003.3589.10.camel@intel.com>\n\t<001d44d1-f54f-04e8-0941-728c34ad3e09@denx.de>","In-Reply-To":"<001d44d1-f54f-04e8-0941-728c34ad3e09@denx.de>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.226.242.102]","Content-ID":"","MIME-Version":"1.0","Cc":"\"See, Chin Liang\" , \"Westergreen,\n\tDalon\" ,\n\t\"skywindctf@gmail.com\" ","Subject":"Re: [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA\n\tprogram header to support Arria 10","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]