Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/818103/?format=api
{ "id": 818103, "url": "http://patchwork.ozlabs.org/api/patches/818103/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-2-git-send-email-tien.fong.chee@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506328815-23733-2-git-send-email-tien.fong.chee@intel.com>", "list_archive_url": null, "date": "2017-09-25T08:39:57", "name": "[U-Boot,v2,01/19] ARM: socfpga: add bindings doc for arria10 fpga manager", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "a7b3148904d13f175fa58a7fbdd95b694b826c65", "submitter": { "id": 70549, "url": "http://patchwork.ozlabs.org/api/people/70549/?format=api", "name": "Chee, Tien Fong", "email": "tien.fong.chee@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-2-git-send-email-tien.fong.chee@intel.com/mbox/", "series": [ { "id": 4901, "url": "http://patchwork.ozlabs.org/api/series/4901/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=4901", "date": "2017-09-25T08:39:56", "name": "Add FPGA, SDRAM, SPL loads U-boot & booting to console", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/4901/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/818103/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/818103/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0yKy0N7mz9tX3\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 25 Sep 2017 18:43:49 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid BBD94C22080; Mon, 25 Sep 2017 08:41:12 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 37A64C21FDD;\n\tMon, 25 Sep 2017 08:40:33 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid E4ADFC21DB5; Mon, 25 Sep 2017 08:40:27 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 7C837C21C8F\n\tfor <u-boot@lists.denx.de>; Mon, 25 Sep 2017 08:40:23 +0000 (UTC)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Sep 2017 01:40:23 -0700", "from tfchee-mobl.gar.corp.intel.com (HELO tienfong.fm.intel.com,\n\t) ([10.226.242.95])\n\tby fmsmga005.fm.intel.com with ESMTP; 25 Sep 2017 01:40:20 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.42,435,1500966000\"; d=\"scan'208\";a=\"155080064\"", "From": "tien.fong.chee@intel.com", "To": "u-boot@lists.denx.de", "Date": "Mon, 25 Sep 2017 16:39:57 +0800", "Message-Id": "<1506328815-23733-2-git-send-email-tien.fong.chee@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>", "References": "<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>", "Cc": "Marek Vasut <marex@denx.de>, Tien Fong Chee <tien.fong.chee@intel.com>, \n\tAlan Tull <atull@opensource.altera.com>,\n\tChing Liang See <chin.liang.see@intel.com>,\n\tTien Fong <skywindctf@gmail.com>, \n\tWestergteen Dalon <dalon.westergreen@intel.com>", "Subject": "[U-Boot] [PATCH v2 01/19] ARM: socfpga: add bindings doc for\n\tarria10 fpga manager", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Tien Fong Chee <tien.fong.chee@intel.com>\n\nThis DT binding doc is porting from Linux DT binding doc.\ncommit 1adcbea4201a6852362aa5ece573f1f169b28113\n\nAdd a device tree bindings document for the SoCFPGA Arria10\nFPGA Manager driver.\n\nSigned-off-by: Alan Tull <atull@opensource.altera.com>\nAcked-by: Rob Herring <robh@kernel.org>\nAcked-By: Moritz Fischer <moritz.fischer@ettus.com>\nSigned-off-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Tien Fong Chee <tien.fong.chee@intel.com>\n---\n .../fpga/altera-socfpga-a10-fpga-mgr.txt | 19 +++++++++++++++++++\n 1 file changed, 19 insertions(+)\n create mode 100644 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt", "diff": "diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\nnew file mode 100644\nindex 0000000..2fd8e7a\n--- /dev/null\n+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n@@ -0,0 +1,19 @@\n+Altera SOCFPGA Arria10 FPGA Manager\n+\n+Required properties:\n+- compatible : should contain \"altr,socfpga-a10-fpga-mgr\"\n+- reg : base address and size for memory mapped io.\n+ - The first index is for FPGA manager register access.\n+ - The second index is for writing FPGA configuration data.\n+- resets : Phandle and reset specifier for the device's reset.\n+- clocks : Clocks used by the device.\n+\n+Example:\n+\n+\tfpga_mgr: fpga-mgr@ffd03000 {\n+\t\tcompatible = \"altr,socfpga-a10-fpga-mgr\";\n+\t\treg = <0xffd03000 0x100\n+\t\t 0xffcfe400 0x20>;\n+\t\tclocks = <&l4_mp_clk>;\n+\t\tresets = <&rst FPGAMGR_RESET>;\n+\t};\n", "prefixes": [ "U-Boot", "v2", "01/19" ] }