[{"id":1774592,"web_url":"http://patchwork.ozlabs.org/comment/1774592/","msgid":"","list_archive_url":null,"date":"2017-09-25T08:59:48","subject":"Re: [U-Boot] [PATCH v2 01/19] ARM: socfpga: add bindings doc for\n\tarria10 fpga manager","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/25/2017 10:39 AM, tien.fong.chee@intel.com wrote:\n> From: Tien Fong Chee \n> \n> This DT binding doc is porting from Linux DT binding doc.\n> commit 1adcbea4201a6852362aa5ece573f1f169b28113\n> \n> Add a device tree bindings document for the SoCFPGA Arria10\n> FPGA Manager driver.\n> \n> Signed-off-by: Alan Tull \n> Acked-by: Rob Herring \n> Acked-By: Moritz Fischer \n> Signed-off-by: Rob Herring \n> Signed-off-by: Tien Fong Chee \n\nApplied, thanks\n\n> ---\n> .../fpga/altera-socfpga-a10-fpga-mgr.txt | 19 +++++++++++++++++++\n> 1 file changed, 19 insertions(+)\n> create mode 100644 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> \n> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> new file mode 100644\n> index 0000000..2fd8e7a\n> --- /dev/null\n> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt\n> @@ -0,0 +1,19 @@\n> +Altera SOCFPGA Arria10 FPGA Manager\n> +\n> +Required properties:\n> +- compatible : should contain \"altr,socfpga-a10-fpga-mgr\"\n> +- reg : base address and size for memory mapped io.\n> + - The first index is for FPGA manager register access.\n> + - The second index is for writing FPGA configuration data.\n> +- resets : Phandle and reset specifier for the device's reset.\n> +- clocks : Clocks used by the device.\n> +\n> +Example:\n> +\n> +\tfpga_mgr: fpga-mgr@ffd03000 {\n> +\t\tcompatible = \"altr,socfpga-a10-fpga-mgr\";\n> +\t\treg = <0xffd03000 0x100\n> +\t\t 0xffcfe400 0x20>;\n> +\t\tclocks = <&l4_mp_clk>;\n> +\t\tresets = <&rst FPGAMGR_RESET>;\n> +\t};\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Mon, 25 Sep 2017 11:58:18 +0200 (CEST)","from [IPv6:::1] (unknown [195.140.253.167])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.mnet-online.de (Postfix) with ESMTPSA;\n\tMon, 25 Sep 2017 11:58:18 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tRCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","X-Virus-Scanned":"amavisd-new at mnet-online.de","X-Auth-Info":"nmR+Mm/3qRnyyLEwOnASZ9dMhzSCvqgDTvMhgoqf4+k=","To":"tien.fong.chee@intel.com, u-boot@lists.denx.de","References":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>\n\t<1506328815-23733-2-git-send-email-tien.fong.chee@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Mon, 25 Sep 2017 10:59:48 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506328815-23733-2-git-send-email-tien.fong.chee@intel.com>","Content-Language":"en-US","Cc":"Alan Tull ,\n\tChing Liang See ,\n\tTien Fong , \n\tWestergteen Dalon ","Subject":"Re: [U-Boot] [PATCH v2 01/19] ARM: socfpga: add bindings doc for\n\tarria10 fpga manager","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; 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