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GET /api/patches/817730/?format=api
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{
    "id": 817730,
    "url": "http://patchwork.ozlabs.org/api/patches/817730/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1506119053-21828-3-git-send-email-tharvey@gateworks.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1506119053-21828-3-git-send-email-tharvey@gateworks.com>",
    "list_archive_url": null,
    "date": "2017-09-22T22:24:11",
    "name": "[2/4] media: dt-bindings: Add bindings for TDA1997X",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "1f1cefbcae5a8dbf251e9d9390229b2d44aa20c1",
    "submitter": {
        "id": 41730,
        "url": "http://patchwork.ozlabs.org/api/people/41730/?format=api",
        "name": "Tim Harvey",
        "email": "tharvey@gateworks.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1506119053-21828-3-git-send-email-tharvey@gateworks.com/mbox/",
    "series": [
        {
            "id": 4716,
            "url": "http://patchwork.ozlabs.org/api/series/4716/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4716",
            "date": "2017-09-22T22:24:09",
            "name": "RFC: TDA1997x HDMI video receiver",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/4716/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/817730/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/817730/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
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        "X-Google-Smtp-Source": "AOwi7QBej+ct5CX0u+DJfj6dHPN+4rAWWiQqks/1luFkAbe2ct1xSm/KWl+Oy5kgiYn6kZOaqnxTNw==",
        "X-Received": "by 10.98.144.155 with SMTP id q27mr471510pfk.275.1506118887794; \n\tFri, 22 Sep 2017 15:21:27 -0700 (PDT)",
        "From": "Tim Harvey <tharvey@gateworks.com>",
        "To": "linux-media@vger.kernel.org",
        "Cc": "devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tshawnguo@kernel.org, Steve Longerbeam <slongerbeam@gmail.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>,\n\tHans Verkuil <hansverk@cisco.com>, \n\tMauro Carvalho Chehab <mchehab@s-opensource.com>",
        "Subject": "[PATCH 2/4] media: dt-bindings: Add bindings for TDA1997X",
        "Date": "Fri, 22 Sep 2017 15:24:11 -0700",
        "Message-Id": "<1506119053-21828-3-git-send-email-tharvey@gateworks.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1506119053-21828-1-git-send-email-tharvey@gateworks.com>",
        "References": "<1506119053-21828-1-git-send-email-tharvey@gateworks.com>",
        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "Signed-off-by: Tim Harvey <tharvey@gateworks.com>\n---\n .../devicetree/bindings/media/i2c/tda1997x.txt     | 159 +++++++++++++++++++++\n 1 file changed, 159 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/i2c/tda1997x.txt",
    "diff": "diff --git a/Documentation/devicetree/bindings/media/i2c/tda1997x.txt b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt\nnew file mode 100644\nindex 0000000..8330733\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/i2c/tda1997x.txt\n@@ -0,0 +1,159 @@\n+Device-Tree bindings for the NXP TDA1997x HDMI receiver\n+\n+The TDA19971/73 are HDMI video receivers.\n+\n+The TDA19971 Video port output pins can be used as follows:\n+ - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]\n+ - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]\n+ - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]\n+ - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]\n+ - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]\n+ - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)\n+ - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)\n+ - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)\n+\n+The TDA19973 Video port output pins can be used as follows:\n+ - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]\n+ - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]\n+ - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]\n+ - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)\n+\n+The Video port output pins are mapped via 4-bit 'pin groups' allowing\n+for a variety fo connection possibilities including swapping pin order within\n+pin groups. The video_portcfg device-tree property consists of register mapping\n+pairs which map a chip-specific VP output register to a 4-bit pin group. If\n+the pin group needs to be bit-swapped you can use the *_S pin-group defines.\n+\n+Required Properties:\n+ - compatible      :\n+  - \"nxp,tda19971\" for the TDA19971\n+  - \"nxp,tda19973\" for the TDA19973\n+ - reg             : I2C slave address\n+ - interrupts      : The interrupt number\n+ - DOVDD-supply    : Digital I/O supply\n+ - DVDD-supply     : Digital Core supply\n+ - AVDD-supply     : Analog supply\n+ - vidout_portcfg  : array of pairs mapping VP output pins to pin groups\n+\n+Optional Properties:\n+ - max-pixel-rate  : Maximum pixel rate supported by the SoC (MP/sec)\n+ - audio-port      : parameters defining audio output port connection\n+\n+Optional Endpoint Properties:\n+  The following three properties are defined in video-interfaces.txt and\n+  are valid for source endpoints only:\n+  - hsync-active: Horizontal synchronization polarity. Defaults to active high.\n+  - vsync-active: Vertical synchronization polarity. Defaults to active high.\n+  - data-active: Data polarity. Defaults to active high.\n+\n+The Audio output port consists of A_CLK, A_WS, AP0, AP1, AP2, and AP3 pins\n+and can support up to 8-chanenl audio using the following audio bus DAI formats:\n+ - I2S16\n+ - I2S32\n+ - SPDIF\n+ - OBA (One-Bit-Audio)\n+ - I2S16_HBR_STRAIGHT (High Bitrate straight through)\n+ - I2S16_HBR_DEMUX (High Bitrate demuxed)\n+ - I2S32_HBR_DEMUX (High Bitrate demuxed)\n+ - DST (Direct Stream Transfer)\n+\n+Audio samples can be output in either SPDIF or I2S bus formats.\n+In I2S mode, the TDF1997X is the master with 16bit or 32bit words.\n+The audio port output is configured by three parameters: DAI format, layout\n+and clock scaler.\n+\n+Each DAI format has two pin layouts shown by the following table:\n+       |  SPDIF  |  SPDIF  |   I2S   |   I2S   |         HBR demux\n+       | Layout0 | Layout1 | Layout0 | Layout1 | SPDIF      | I2S\n+ ------+---------+---------+---------+---------+------------+------------\n+ A_WS  | WS      | WS      | WS      | WS      | WS         | WS\n+ AP3   |         | SPDIF3  |         | SD3     | SPDIF[x+3] | SD[x+3]\n+ AP2   |         | SPDIF2  |         | SD2     | SPDIF[x+2] | SD[x+2]\n+ AP1   |         | SPDIF1  |         | SD1     | SPDIF[x+1] | SD[x+1]\n+ AP0   | SPDIF   | SPDIF0  | SD      | SD0     | SPDIF[x]   | SD[x]\n+ A_CLK | (32*Fs) | (32*Fs) |(32*Fs)  | (32*Fs) | (32*Fs)    | (32*Fs)\n+       | (64*Fs) | (64*Fs) |(64*Fs)  | (64*Fs) | (64*Fs)    | (64*Fs)\n+\n+Freq(Sysclk) = 2*freq(Aclk)\n+\n+Examples:\n+ - VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422\n+   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)\n+\thdmi_receiver@48 {\n+\t\tcompatible = \"nxp,tda19971\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_tda1997x>;\n+\t\treg = <0x48>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <7 IRQ_TYPE_LEVEL_LOW>;\n+\t\tDOVDD-supply = <&reg_3p3v>;\n+\t\tAVDD-supply = <&reg_1p8v>;\n+\t\tDVDD-supply = <&reg_1p8v>;\n+\t\t/* audio output format */\n+\t\taudio-port = < TDA1997X_I2S16\n+\t\t\t       TDA1997X_LAYOUT0\n+\t\t\t       TDA1997X_ACLK_128FS >;\n+\t\t/*\n+\t\t * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]\n+\t\t * and Y[11:4] across 16bits in the same pixclk cycle.\n+\t\t */\n+\t\tvidout_portcfg =\n+\t\t\t/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */\n+\t\t\t< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,\n+\t\t\t/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */\n+\t\t\t< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,\n+\t\t\t/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */\n+\t\t\t< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,\n+\t\t\t/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */\n+\t\t\t< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;\n+\t\tmax-pixel-rate = <180>; /* IMX6 CSI max pixel rate 180MP/sec */\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t};\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\thdmi_in: endpoint {\n+\t\t\t\tremote-endpoint = <&ccdc_in>;\n+\t\t\t};\n+\t\t};\n+\t};\n+ - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656\n+   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)\n+\thdmi_receiver@48 {\n+\t\tcompatible = \"nxp,tda19971\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_tda1997x>;\n+\t\treg = <0x48>;\n+\t\tinterrupt-parent = <&gpio1>;\n+\t\tinterrupts = <7 IRQ_TYPE_LEVEL_LOW>;\n+\t\tDOVDD-supply = <&reg_3p3v>;\n+\t\tAVDD-supply = <&reg_1p8v>;\n+\t\tDVDD-supply = <&reg_1p8v>;\n+\t\t/* audio output format */\n+\t\t#sound-dai-cells = <0>;\n+\t\taudio-port = < TDA1997X_I2S16\n+\t\t\t       TDA1997X_LAYOUT0\n+\t\t\t       TDA1997X_ACLK_128FS >;\n+\t\t/*\n+\t\t * The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over\n+\t\t * 2 pixclk cycles.\n+\t\t */\n+\t\tvidout_portcfg =\n+\t\t\t/* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */\n+\t\t\t< TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >,\n+\t\t\t/* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */\n+\t\t\t< TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >,\n+\t\tmax-pixel-rate = <180>; /* IMX6 CSI max pixel rate 180MP/sec */\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\t\t};\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\t\t\thdmi_in: endpoint {\n+\t\t\t\tremote-endpoint = <&ccdc_in>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n",
    "prefixes": [
        "2/4"
    ]
}