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GET /api/patches/817657/?format=api
{ "id": 817657, "url": "http://patchwork.ozlabs.org/api/patches/817657/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170922171323.10348-5-f4bug@amsat.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170922171323.10348-5-f4bug@amsat.org>", "list_archive_url": null, "date": "2017-09-22T17:13:20", "name": "[v5,4/7] hw/mdio: Mask out read-only bits.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b08ee0523af56592796c3089f2831e852471f46f", "submitter": { "id": 70924, "url": "http://patchwork.ozlabs.org/api/people/70924/?format=api", "name": "Philippe Mathieu-Daudé", "email": "f4bug@amsat.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170922171323.10348-5-f4bug@amsat.org/mbox/", "series": [ { "id": 4680, "url": "http://patchwork.ozlabs.org/api/series/4680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4680", "date": "2017-09-22T17:13:16", "name": "Generalize MDIO framework", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/4680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817657/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817657/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ZcfO/pze\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzKvm23mzz9sP1\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 23 Sep 2017 03:19:00 +1000 (AEST)", "from localhost ([::1]:60303 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dvRbN-000827-TM\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 13:18:57 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:59406)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dvRWT-0003WF-NI\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 13:13:54 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dvRWR-0003Vg-Kl\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 13:13:53 -0400", "from mail-qk0-x241.google.com ([2607:f8b0:400d:c09::241]:38070)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <philippe.mathieu.daude@gmail.com>)\n\tid 1dvRWR-0003VW-Gn\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 13:13:51 -0400", "by mail-qk0-x241.google.com with SMTP id c69so1021460qke.5\n\tfor <qemu-devel@nongnu.org>; Fri, 22 Sep 2017 10:13:51 -0700 (PDT)", "from yoga.lan ([181.93.89.178]) by smtp.gmail.com with ESMTPSA id\n\tf69sm238468qke.27.2017.09.22.10.13.48\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 22 Sep 2017 10:13:50 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=rxMyLB2uMtPH+zMkI5VbbZoqC3EDT+m6CVY44lTEBi4=;\n\tb=ZcfO/pzeZwwQivDlrW2iP1XSRNNOnI2VnAJYWjvF883p0QyuL/9o4RkxguUYK81YIg\n\twHRvTsy2LD0CNakWA5xEPi76v9LEM+R0QXmCZf+5/W3/P4MZ1IcPBKP3kXDUKWJnEaLL\n\tMgctFPGV4ZyIW5zwW2NM1tYjsM6BKXvBpPr2kv5k/URPpsJ+bCyJaT0r+EKPSyNjG+79\n\tpJbCLetur5NINhn4YjRO2xN5TdJFY2K6x8Qty92lexhPnvxk7P2P4YWc6yEyGuogSZPm\n\ta7yde52mR4QeeB5DvUE39X2uFR1lTKPL90ucBWQTRIgkpcXQG/BEZebs2SUghK04SwQ+\n\t0dTQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references:mime-version:content-transfer-encoding;\n\tbh=rxMyLB2uMtPH+zMkI5VbbZoqC3EDT+m6CVY44lTEBi4=;\n\tb=gn4rQOE7fULbb33aXM8bOsFW6Go3cCXvNNAwDxBxx30AYbpc4nkbVu0QvYmM+ltMNj\n\tV2CsYijAhh9lWCuP5u4c+iIuCBiyjHfcatzW014ibVUkB8l7BtP7Wtn4rbj5WuMU9uBo\n\tV+3zfA8qQLI3Kd+9UXx1Ug0wnNAkaVHyYSZNotd6HirmUwoq4ykWS5Dm/67+2LtjMYac\n\tahaklNRlrYOgWDD6S6vBfnKHIzYn+M92jo1Yj7+7Ixz8caCFCFSRfLprPKvI/diSOOAy\n\tA4Xj/WoyHBAd1m09oJEglUQ42WsFufwxr+IUaBUapjw2ZzRWj6ByWUw9dQj1Hb9SaDYq\n\t5aRw==", "X-Gm-Message-State": "AHPjjUgzgwhfCFCXBJnc9Nf+jWUC8AIE1wT44DRlCHREJTC2lOWlnkwB\n\tp8JxUeYmDAMlsRaq1XZQ5fo=", "X-Google-Smtp-Source": "AOwi7QCvjnvA+3j/ZRTK/+ZALDhOvHyc1f7sbh3T9jWSxIiSfer3ncRVhuWQWl3YPfubtZBhE43JTQ==", "X-Received": "by 10.55.87.135 with SMTP id l129mr9063888qkb.182.1506100431003; \n\tFri, 22 Sep 2017 10:13:51 -0700 (PDT)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org>", "To": "Peter Maydell <peter.maydell@linaro.org>,\n\tGrant Likely <grant.likely@arm.com>, Jason Wang <jasowang@redhat.com>", "Date": "Fri, 22 Sep 2017 14:13:20 -0300", "Message-Id": "<20170922171323.10348-5-f4bug@amsat.org>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170922171323.10348-1-f4bug@amsat.org>", "References": "<20170922171323.10348-1-f4bug@amsat.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400d:c09::241", "Subject": "[Qemu-devel] [PATCH v5 4/7] hw/mdio: Mask out read-only bits.", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "qemu-devel@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=\n\t<f4bug@amsat.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Grant Likely <grant.likely@arm.com>\n\nThe RST and ANEG_RST bits are commands, not settings. An operating\nsystem will get confused (or at least u-boot does) if those bits remain\nset after writing to them. Therefore, mask them out on write.\n\nSimilarly, no bits in the ID1, ID2, and remote capability registers are\nwriteable; so mask them out also.\n\nSigned-off-by: Grant Likely <grant.likely@arm.com>\nSigned-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>\n[PMD: just rebased]\n---\n include/hw/net/mdio.h | 1 +\n hw/net/mdio.c | 16 ++++++++++++----\n 2 files changed, 13 insertions(+), 4 deletions(-)", "diff": "diff --git a/include/hw/net/mdio.h b/include/hw/net/mdio.h\nindex b3b4f497c0..ed1879a728 100644\n--- a/include/hw/net/mdio.h\n+++ b/include/hw/net/mdio.h\n@@ -53,6 +53,7 @@\n \n struct qemu_phy {\n uint32_t regs[NUM_PHY_REGS];\n+ const uint16_t *regs_readonly_mask; /* 0=writable, 1=read-only */\n \n int link;\n \ndiff --git a/hw/net/mdio.c b/hw/net/mdio.c\nindex 33bfbb4623..89a6a3a590 100644\n--- a/hw/net/mdio.c\n+++ b/hw/net/mdio.c\n@@ -109,17 +109,24 @@ static unsigned int mdio_phy_read(struct qemu_phy *phy, unsigned int req)\n \n static void mdio_phy_write(struct qemu_phy *phy, unsigned int req, unsigned int data)\n {\n- int regnum;\n+ int regnum = req & 0x1f;\n+ uint16_t mask = phy->regs_readonly_mask[regnum];\n \n- regnum = req & 0x1f;\n- D(printf(\"%s reg[%d] = %x\\n\", __func__, regnum, data));\n+ D(printf(\"%s reg[%d] = %x; mask=%x\\n\", __func__, regnum, data, mask));\n switch (regnum) {\n default:\n- phy->regs[regnum] = data;\n+ phy->regs[regnum] = (phy->regs[regnum] & mask) | (data & ~mask);\n break;\n }\n }\n \n+static const uint16_t default_readonly_mask[32] = {\n+ [PHY_CTRL] = PHY_CTRL_RST | PHY_CTRL_ANEG_RST,\n+ [PHY_ID1] = 0xffff,\n+ [PHY_ID2] = 0xffff,\n+ [PHY_LP_ABILITY] = 0xffff,\n+};\n+\n void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)\n {\n phy->regs[PHY_CTRL] = 0x3100;\n@@ -128,6 +135,7 @@ void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)\n phy->regs[PHY_ID2] = id2;\n /* Autonegotiation advertisement reg. */\n phy->regs[PHY_AUTONEG_ADV] = 0x01e1;\n+ phy->regs_readonly_mask = default_readonly_mask;\n phy->link = 1;\n \n phy->read = mdio_phy_read;\n", "prefixes": [ "v5", "4/7" ] }